Fujitsu FR81S User Manual
CHAPTER 11: I/O PORTS
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : I/O PORTS
FUJITSU SEMICONDUCTOR CONFIDENTIAL
44
4.7. Port Input Enable Register: PORTEN (PORT ENable
register)
The bit configuration of the port input enable register is shown below.
This register contains control-bit to enable port input. At a power-on reset, inputs to most pins are blocked
in order to avoid pass-through current fluctuations before the ports are configured by software. For
information on pins whose inputs are blocked, see "D. Pin status in CPU Status" in "APPENDIX". After
each port pin is configured for its function by software, Global PORT Enable (PORTEN.GPORTEN) bit
must be set to “1” to enable input.
PORTEN : Address 0F40
H
(Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved
GPORTEN
Initial
value
1
1
1
1
1
1
0
0
Attribute R1,WX R1,WX R1,WX R1,WX R1,WX R1,WX
R/W
R/W
[bit0] GPORTEN (Global PORT ENable) : Global input enable
GPORTEN
Operation
0
Most of pins are set input-blocked to cut off pass-through current at
unstable condition. See "Pin status in CPU Status" in "APPENDIX"
for the pin that is input-blocked at initial state by reset.
1
The input is enabled by this bit.
MB91520 Series
MN705-00010-1v0-E
439