Fujitsu FR81S User Manual
CHAPTER 12: INTERRUPT CONTROL (INTERRUPT
CONTROLLER)
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: INTERRUPT CONTROL (INTERRUPT CONTROLLER)
FUJITSU SEMICONDUCTOR CONFIDENTIAL
7
4.1. Interrupt Control Registers 00 to 47 : ICR00 to ICR47
(Interrupt Control Register 00 to 47):
The bit configuration of the interrupt control registers 00 to 47 is shown below.
One register is provided for each interrupt input to set the level for the corresponding interrupt request.
ICR00 to ICR47 : Address 0440
H
to 046F
H
(Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved
IL[4:0]
Initial value
1
1
1
1
1
1
1
1
Attribute R1,WX R1,WX R1,WX R1,WX
R/W
R/W
R/W
R/W
[bit4 to bit0] IL[4:0] (Interrupt Level control)
The interrupt level setting bits specify the interrupt level for the corresponding interrupt request. An interrupt
request is masked in the CPU if the interrupt level set in these registers is greater than or equal to the level
mask value in the ILM register of the CPU. These bits are initialized to "5’b11111" on reset.
The correspondence between the configurable interrupt level settings bits and the interrupt levels is shown
below.
IL[4:0]
Interrupt level
10000
16
Configurable highest level
10001
17
↑
(High)
10010
18
|
10011
19
|
10100
20
|
10101
21
|
10110
22
|
10111
23
|
11000
24
|
11001
25
|
11010
26
|
11011
27
|
11100
28
|
11101
29
|
11110
30
↓
(Low)
11111
31
Interrupts disabled
IL4 is fixed at 1 Writing has no effect.
MB91520 Series
MN705-00010-1v0-E
468