Fujitsu FR81S User Manual

CHAPTER 20: RELOAD TIMER

6. Application Note

FUJITSU SEMICONDUCTOR LIMITED

CHAPTER : RELOAD TIMER
FUJITSU SEMICONDUCTOR CONFIDENTIAL

3. When using TIN input as a trigger input

TMCSR

TMRLRA TMRLRB

MOD

[1:0]

TRGM

[1:0]

CSL

[2:0]

GATE EF OUTL RELD INTE

UF CNTE TRG

(A)

(B)

(A): The count initial value at an activation trigger/The reload value at an underflow caused by the count
from the TMRLRB value (when RELD=1)
(B): The reload value at an underflow caused by the count from the TMRLRA value
S :Use at timer activation
-:Does not influence operation
*1: TIN effective edge setting

TRGM[1:0]= 00------Does not detect external trigger edge

TRGM[1:0]= 01------Rising edge

TRGM[1:0]= 10------Falling edge

TRGM[1:0]= 11------Both edges

*2:Count clock division setting

CSL[2:0]= 000------Division of peripheral clock (PCLK) by 2

CSL[2:0]= 010------Division of peripheral clock (PCLK) by 8

CSL[2:0]= 011------Division of peripheral clock (PCLK) by 16

CSL[2:0]= 100------Division of peripheral clock (PCLK) by 32

CSL[2:0]= 101------Division of peripheral clock (PCLK) by 64

*3:TOUT output polarity setting

OUTL= 0------Initial value L=> Count L from TMRLRA => Invert whenever an underflow occurs

OUTL= 1------Initial value H=> Count H from TMRLRA => Invert whenever an underflow occurs

*4:Reload setting when an underflow occurs

RELD=0------One-shot mode

RELD=1------Reload mode

*5:Interrupt request enable setting

INTE=0------Interrupt disabled

INTE=1------Interrupt enabled

[Timer activation] Follow the steps below to activate the timer.

⋅ Input an activation trigger (a write of "1" to the TRG bit or an input of effective external edge from TIN

pin)

⋅ Input an effective level when you use TIN pin input as the gate input

Figure 6-4 Example of Operation (OUTL=0)

TOUT

(TMRLRA + 1)

(TMRLRB + 1)

Counter value

TMPLRA

0000

TMRLRB

0x0000

TMRLRA

Activation trigger
Underflow

Downcount

MB91520 Series

MN705-00010-1v0-E

790