Fujitsu FR81S User Manual
CHAPTER 21: 32-BIT FREE-RUN TIMER
3. Configuration
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: 32-BIT FREE-RUN TIMER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
8
3.1. Configuration diagram of the 32-bit free-run timer
The configuration diagram of the 32-bit free-run timer is shown.
Figure 3-1 Configuration Diagram of the 32-bit free-run timer (only one channel)
CLKP
CLKP / 2
CLKP / 4
CLKP / 8
CLKP / 16
CLKP / 32
CLKP / 64
CLKP / 128
CLKP / 256
Peripheral clock
(PCLK)
Divider
Setting is prohibited
Clock selection
Compare clear match flag
Count clock
Timer data register n
Compare clear register n
Cancel timer initialization clear request
Timer clear
Counting operation
No interrupt request
Disable interrupt
Free-run timer
interrupt
Interrupt request
WRITE 0: Flag clear
Counting operation stop
Internal clock
Count
value
Clear
C
om
par
e
ci
rc
ui
t
External clock
synchronization
circuit
n=3 to 5
To input capture and
output compare
CLK[3:0]
TCCSn : bit3-0
ECKE
TCCSn:bit15
SCLR
TCCSn:bit4
STOP TCCSn:bit6
TCCSn:bit9
ICRE
ICLR
TCCSn:bit8
TCDTn
CPCLRn
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
0 1 1 1
0 1 0 0
0 1 0 1
1 0 0 0
0 1 1 0
FRCKn
1
Enable interrupt
External clock
0
MB91520 Series
MN705-00010-1v0-E
803