Fujitsu FR81S User Manual
CHAPTER 21: 32-BIT FREE-RUN TIMER
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: 32-BIT FREE-RUN TIMER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
12
4.1.1. Timer Control Register (Upper Bit) : TCCSH
The bit configuration of the timer control register (Upper bit) is shown.
This register is used to control the operation of the free-run timer.
TCCSH3-5 (Free-run timer 3-5): Address Base_addr+08
H
(Access: Byte,
Half-word, Word)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
ECKE
-
-
-
-
-
ICLR
ICRE
Initial value
0
0
0
0
0
0
0
0
Attribute
R/W
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX R(RM1),W
R/W
[bit15] ECKE : Clock selection
ECKE
Count clock selection
0
Internal clock
1
External clock (FRCK)
⋅
When this bit is set to "0": Internal clock is selected. To select the count clock frequency, you will also
need to select the clock frequency selection bits (CLK3 to CLK0:bit3 to bit0) of the TCCSL register.
⋅
When this bit is set to "1": External clock is selected. The external clock is input from the "FRCK" pin.
Therefore, enable external clock input by writing "0" to the bit of the port direction register (DDR)
corresponding to the FRCK input pin and writing "0" to the bit of the corresponding port function
register (PFR) to switch to port input state. If external clock is selected by the ECKE bit, clock count will
detect both edges. Set the pulse width of the external clock to 4/F
PCLK
or more.
Note:
The setting change for the count clock selection bit must be performed while other peripheral modules using
the free-run timer output (output compare and input capture) are inactive.
[bit14 to bit10] - : Undefined
The read value is always "0". This does not affect the writing operation.
[bit9] ICLR : Compare clear interrupt flag
ICLR
State
Read
Write
0
No compare clear match
Clear the flag (ICLR)
1
Compare clear match
No effect on operation
⋅
This bit will be set to "1" when the compare clear value matches the 32-bit free-run timer value.
MB91520 Series
MN705-00010-1v0-E
807