Nortel Networks MSC8101 ADS User Manual

C-118

MOTOROLA

  --  with default MODCK setting from DIP-Switch 
  --  PONRESET pulse resets while WD. 
  --  Implemented as ripple counter with 30 stages

-- WDEn.s = GND; WDEn.r = GND;
-- WDEn.prn = !(MPC_WRITE_BCSR_4 & (D[0..1] == B”10”)); 
  -- Preset to FF when write b’10 bit to BCSR4 
-- WDEn.clrn = !END_OF_WD_TIMER & !MPC_READ_BCSR_4 & PRST~;
CLEAR_TO_WD_CTRL = LCELL (PRST~);
StartStopWD.clrn = CLEAR_TO_WD_CTRL;
StartStopWD.clk = !(MPC_WRITE_BCSR_4 & (D[0..1] == B”01”));
StartStopWD.s = VCC; StartStopWD.r = VCC; ---- Provide toggling

END_OF_WD_TIMER = WD_TIMER1.dv2 & WD_TIMER1.dv4 & WD_TIMER1.dv8 & WD_TIMER1.dv16 & 
                  WD_TIMER2.dv2 & WD_TIMER2.dv4 & WD_TIMER2.dv8 & WD_TIMER2.dv16 &
                  WD_TIMER3.dv2 & WD_TIMER3.dv4 & WD_TIMER3.dv8 & WD_TIMER3.dv16 &
                  WD_TIMER4.dv2 & WD_TIMER4.dv4 & WD_TIMER4.dv8 & WD_TIMER4.dv16 &
                  WD_TIMER5.dv2 & WD_TIMER5.dv4 & WD_TIMER5.dv8 & WD_TIMER5.dv16 &
                  WD_TIMER6.dv2 & WD_TIMER6.dv4 & WD_TIMER6.dv8 & WD_TIMER6.dv16 &
                  WD_TIMER7.dv2 & WD_TIMER7.dv4 & WD_TIMER7.dv8 & WD_TIMER7.dv16 &
                  WD_TIMER8.dv2 & WD_TIMER8.dv4;
WD_TIMER1.g = StartStopWD.q; WD_TIMER2.g = StartStopWD.q; WD_TIMER3.g = StartStopWD.q; WD_TIMER4.g =
StartStopWD.q;
WD_TIMER5.g = StartStopWD.q; WD_TIMER6.g = StartStopWD.q; WD_TIMER7.g = StartStopWD.q; WD_TIMER8.g =
StartStopWD.q;

WD_TIMER2.clk = WD_TIMER1.dv16; -- Cascade
WD_TIMER3.clk = WD_TIMER2.dv16; -- Cascade
WD_TIMER4.clk = WD_TIMER3.dv16; -- Cascade
WD_TIMER5.clk = WD_TIMER4.dv16; -- Cascade
WD_TIMER6.clk = WD_TIMER5.dv16; -- Cascade
WD_TIMER7.clk = WD_TIMER6.dv16; -- Cascade
WD_TIMER8.clk = WD_TIMER7.dv16; -- Cascade

HRESET_FEdge.clock = Extclk;
HRESET_FEdge.aclr = HRESET~ OR !R_PORI~;
IF(HRESET_FEdge.q[] == 3) THEN HRESET_FEdge.cnt_en = GND; -- Disable count after term value
 ELSE                          HRESET_FEdge.cnt_en = VCC; 
END IF;

RESETS = (HRESET_FEdge.q[] == 1) OR (HRESET_FEdge.q[] == 2) OR 
         !(R_PORI~ & PRST~);
  
WD_TIMER1.clr = RESETS; -- Reset first cascade divider
WD_TIMER2.clr = RESETS; -- Reset second cascade divider
WD_TIMER3.clr = RESETS; -- Reset third cascade divider
WD_TIMER4.clr = RESETS; -- Reset forth cascade divider
WD_TIMER5.clr = RESETS; -- Reset third cascade divider
WD_TIMER6.clr = RESETS; -- Reset forth cascade divider
WD_TIMER7.clr = RESETS; -- Reset forth cascade divider
WD_TIMER8.clr = RESETS; -- Reset forth cascade divider

SPARE1 = (HRESET_FEdge.q[] == 1) OR (HRESET_FEdge.q[] == 2);
%
******************************************************************************
%
END;-- End of BCSR module

F

re

e

sc

a

le

 S

e

m

ic

o

n

d

u

c

to

r,

 I

  

  

  

  

  

  

  

  

  

  

  

  

  

  

  

  

  

  

  

  

  

  

  

 

Freescale Semiconductor, Inc.

For More Information On This Product,

   Go to: www.freescale.com

n

c

.

..