Intel GD82559ER User Manual
Datasheet
57
Networking Silicon — GD82559ER
8.
Control/Status Registers
8.1
LAN (Ethernet) Control/Status Registers
The 82559ER’s Control/Status Register (CSR) is illustrated in the figure below.
NOTE: In
Figure 23
above, SCB is defined as the System Control Block of the 82559ER, and PMDR is defined
as the Power Management Driver Register.
SCB Status Word:
The 82559ER places the status of its Command and Receive units
and interrupt indications in this register for the CPU to read.
and interrupt indications in this register for the CPU to read.
SCB Command Word:
The CPU places commands for the Command and Receive units in
this register. Interrupts are also acknowledged in this register.
this register. Interrupts are also acknowledged in this register.
SCB General Pointer:
The SCB General Pointer register points to various data structures
in main memory depending on the current SCB Command word.
in main memory depending on the current SCB Command word.
PORT Interface:
The PORT interface allows the CPU to reset the 82559ER, force the
82559ER to dump information to main memory, or perform an
internal self test.
82559ER to dump information to main memory, or perform an
internal self test.
Flash Control Register:
The Flash Control register allows the CPU to enable writes to an
external Flash.
external Flash.
EEPROM Control Register: The EEPROM Control register allows the CPU to read and write to
an external EEPROM.
D31 Upper Word D16
D15 Lower Word D0
Offset
SCB Command Word
SCB Status Word
00H
System Control Block General Pointer
04H
PORT
08H
EEPROM Control Register
Flash Control Register
0CH
Management Data Interface (MDI) Control Register
10H
Receive Direct Memory Access Byte Count
14H
PMDR
Flow Control Register
Early Receive Int
18H
Reserved
General Status
General Control
1CH
Reserved
20H
Reserved
24H
Reserved
28H
Reserved
2CH
Reserved
30H
Reserved
34H
Reserved
38H
Reserved
3CH
Figure 23. 82559ER Control/Status Register