Panasonic MN103001G/F01K User Manual
Bus Controller (BC)
8-28
8.8
Operation Clocks
MCLK, IOCLK, and SYSCLK are used as BC operation clocks. Table 8-8-1 shows the ratio of each clock versus
the oscillation input clock (OSCI).
the oscillation input clock (OSCI).
Table 8-8-1
Frequency Ratios of BC Operation Clocks
Oscillation mode
Clock control register setting
SYSCLK
MCLK
IOCLK
CKSEL
PLL
mutiplier
mutiplier
mutiplier
MCK[1:0] = 10
4
1
H
Using
MCK[1:0] = 01
1
2
1/2
MCK[1:0] = 00
1
1/4
L
Not using
Not using
1/2
1/2
1/8
For details, refer to Chapter 6, “Clock Generator.”
8.9
Mode Settings
The values of external input pins MMOD1 to 0 and EXMOD1 to 0 set the external memory mode, block 0 bus
width, and separate/common mode for the address pins and data pins. The various mode settings that can be made
through the external pins are shown in Table 8-9-1.
width, and separate/common mode for the address pins and data pins. The various mode settings that can be made
through the external pins are shown in Table 8-9-1.
Table 8-9-1
Mode Settings by the BC External Pins
Selection
Setting
Mode name
Address/data Block 0 bus width*
MMOD1
MMOD0
EXMOD1
EXMOD0
Separate
8 bits
L
H
L
L
Memory extension mode
16 bits
L
H
L
H
Common
8 bits
L
H
H
L
16 bits
L
H
H
H
Separate
8 bits
H
L
L
L
Processor mode
16 bits
H
L
L
H
Common
8 bits
H
L
H
L
16 bits
H
L
H
H
* Set the bus widths for blocks 1 to 3 through their respective memory control registers.