Panasonic MN103001G/F01K User Manual
Bus Controller (BC)
8-30
8.11 Store Buffer
The bus controller has one store buffer (with a 32-bit data width) built in, and is used to avoid a time penalty when
conducting a store operation in internal I/O or external memory. The CPU store operation is completed storing the
address, data, and access size in the store buffer, and is executed with no wait states. Writes from the store buffer
address, data, and access size in the store buffer, and is executed with no wait states. Writes from the store buffer
to internal I/O or external memory are conducted in parallel with subsequent CPU operations. However, if there is
a request from the CPU for an access to the internal I/O or external memory before the write from the store buffer
a request from the CPU for an access to the internal I/O or external memory before the write from the store buffer
is completed, execution of that request is delayed.