Panasonic MN103001G/F01K User Manual

2-2

CPU

• Structure

Load/store architecture
Data/Address/SP Registers x 9
(Data registers: 32-bit x 4, Address registers: 32-bit x 4, SP: 32-bit x 1)
Other Registers

(PC: 32-bit x 1, PSW: 16-bit x 1, Multiply/divide register: 32-bit x 1,

Branch target registers: 32-bit x 2)

• Instructions

Number of instructions

: 46

Number of addressing modes

: 6

Basic instruction length

: 1 byte

Code assignment

: 1 byte to 2 bytes (basic part)

+ 0 byte to 6 bytes (extension)

• Basic performance

Maximum internal operating

frequency

: 60 MHz*

1

 (external oscillation: 15 MHz)

40 MHz*

2

 (external oscillation: 10 MHz)

Minimum instruction execution
cycle

: 1 cycle (16.7 ns*

1

/25 ns*

2

)

Register-register operations

: 1 cycle

Load/store

: 1 cycle

Conditional branch

: 1 cycle to 3 cycles

• Pipeline

5-stage (Instruction fetch, decode, execute, memory access, write-back)

• Address space

4 GB
Unified space for instructions and data
(Instructions can not be read from internal data RAM.)

*

1

 

in the case of the MN103001G.

*

2

 

in the case of the MN1030F01K.