Panasonic MN103001G/F01K User Manual

2-4

CPU

31

D0
D1
D2
D3

0

31

A0
A1
A2
A3

0

31

SP

0

31

PC

0

31

MDR

0

15

PSW

0

31

LIR

0

31

LAR

0

Data Register

Address Register

Stack Pointer

Program Counter

Multiply/Divide Register

Processor Status Word

Loop Instruction Register

Loop Address Register

Fig. 2-3-1   CPU Registers

2.3.1 CPU Registers

• The register set is divided into data registers that are used for arithmetic operations, etc., address registers that

are used for pointers, and a stack pointer.  This arrangement contributes greatly to the improved performance of
the internal architecture, through reduction of instruction code size, improved parallelism in pipeline processing,

etc.

• This register enables programming in C and other high-level languages.

• The loop instruction register (LIR) and the loop address register (LAR) are used to provide high-speed execution

of branch instructions.  High-speed loop control is performed by loading the branch target instruction and following

fetch address with the SETLB instruction and forming the loop using the Lcc instruction.