Texas Instruments TMS320DM357 User Manual
4.27 Receive Buffer Count 1 Register (RBUFCNT1)
4.28 Receive Buffer Count 2 Register (RBUFCNT2)
Registers
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The Receive Buffer Count 1 Register (RBUFCNT1) is shown in
and described in
Figure 42. Receive Buffer Count 1 Register (RBUFCNT1)
31
16
Reserved
R-0
15
0
BUFCNT
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 43. Receive Buffer Count 1 Register (RBUFCNT1) Field Descriptions
Bit
Field
Value
Description
31-16
Reserved
0
Reserved
15-0
BUFCNT
0-FFFFh
Receive CPPI Buffer Count
The current count of CPPI buffers in Receive channel 1 queue. Writes add to current value (not
overwrite). The DMA requires a minimum of 3 RX buffers to operate.
overwrite). The DMA requires a minimum of 3 RX buffers to operate.
The Receive Buffer Count 2 Register (RBUFCNT2) is shown in
and described in
Figure 43. Receive Buffer Count 2 Register (RBUFCNT2)
31
16
Reserved
R-0
15
0
BUFCNT
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 44. Receive Buffer Count 2 Register (RBUFCNT2) Field Descriptions
Bit
Field
Value
Description
31-16
Reserved
0
Reserved
15-0
BUFCNT
0-FFFFh
Receive CPPI Buffer Count
The current count of CPPI buffers in Receive channel 2 queue. Writes add to current value (not
overwrite). The DMA requires a minimum of 3 RX buffers to operate.
overwrite). The DMA requires a minimum of 3 RX buffers to operate.
Universal Serial Bus (USB) Controller
100
SPRUGH3 – November 2008