User ManualTable of ContentsTable of Contents3Preface111 Introduction141.1 Purpose of the Peripheral141.2 Features141.3 Features Not Supported141.4 Functional Block Diagram151.5 Supported Use Case Examples161.6 Industry Standard(s) Compliance Statement222 Peripheral Architecture232.1 Clock Control232.2 Signal Descriptions232.3 Indexed and Non-Indexed Registers232.4 USB PHY Initialization242.5 Dynamic FIFO Sizing243 USB Controller Host and Peripheral Modes Operation243.1 USB Controller Peripheral Mode Operation263.1.1 Peripheral Mode: Control Transactions263.1.1.1 Zero Data Requests273.1.1.2 Write Requests273.1.1.3 Read Requests283.1.1.4 Endpoint 0 States293.1.1.5 Endpoint 0 Service Routine313.1.2 Bulk Transactions373.1.2.1 Peripheral Mode: Bulk In Transactions373.1.2.2 Peripheral Mode: Bulk OUT Transactions383.1.3 Interrupt Transactions403.1.4 Isochronous Transactions413.1.4.1 Isochronous IN Transactions413.1.4.2 Isochronous OUT Transactions423.2 USB Controller Host Mode Operation443.2.1 Host Mode: Control Transactions443.2.1.1 Setup Phase453.2.1.2 IN Data Phase463.2.1.3 OUT Data Phase473.2.1.4 IN Status Phase (following SETUP Phase or OUT Data Phase)493.2.1.5 OUT Status Phase (following IN Data Phase)503.2.2 Bulk Transactions523.2.2.1 Host Mode: Bulk IN Transactions523.2.2.2 Bulk OUT Transactions533.2.3 Host Mode: Interrupt Transactions543.2.4 Isochronous Transactions553.2.4.1 Host Mode: Isochronous IN Transactions553.2.4.2 Host Mode: Isochronous Out Transactions563.3 DMA Operation573.3.1 DMA Transmit Operation573.3.1.1 Transmit Buffer573.3.1.2 CPPI Transmit Buffer Descriptor573.3.1.3 Transmit DMA State593.3.1.4 Transmit Queue603.3.1.5 Operation603.3.1.6 Transparent Mode and RNDIS Mode Transmit DMA Operation613.3.1.7 DMA Channel TearDown623.3.2 DMA Receive Operation623.3.2.1 Receive Buffer623.3.2.2 CPPI Receive Buffer Descriptor633.3.2.3 Receive DMA State643.3.2.4 Receive Queue653.3.2.5 Operation653.3.2.6 Receive Abort Handling673.3.2.7 RNDIS Mode and Transparent Mode Receive DMA Operation673.3.2.8 DMA Teardown Procedure683.4 Interrupt Handling683.4.1 USB Core Interrupts703.4.2 DMA Interrupts703.5 Test Modes703.5.1 TEST_SE0_NAK713.5.2 TEST_J713.5.3 TEST_K713.5.4 TEST_PACKET723.5.5 FIFO_ACCESS723.5.6 FORCE_HOST733.6 Reset Considerations743.6.1 Software Reset Considerations743.6.2 Hardware Reset Considerations743.6.3 USB Reset Considerations743.7 Interrupt Support743.8 EDMA Event Support743.9 Power Management744 Registers754.1 Control Register (CTRLR)824.2 Status Register (STATR)834.3 RNDIS Register (RNDISR)834.4 Auto Request Register (AUTOREQ)844.5 USB Interrupt Source Register (INTSRCR)854.6 USB Interrupt Source Set Register (INTSETR)864.7 USB Interrupt Source Clear Register (INTCLRR)874.8 USB Interrupt Mask Register (INTMSKR)884.9 USB Interrupt Mask Set Register (INTMSKSETR)894.10 USB Interrupt Mask Clear Register (INTMSKCLRR)904.11 USB Interrupt Source Masked Register (INTMASKEDR)914.12 USB End of Interrupt Register (EOIR)924.13 USB Interrupt Vector Register (INTVECTR)924.14 Transmit CPPI Control Register (TCPPICR)934.15 Transmit CPPI Teardown Register (TCPPITDR)934.16 CPPI DMA End of Interrupt Register (CPPIEOIR)944.17 Transmit CPPI Masked Status Register (TCPPIMSKSR)954.18 Transmit CPPI Raw Status Register (TCPPIRAWSR)954.19 Transmit CPPI Interrupt Enable Set Register (TCPPIIENSETR)964.20 Transmit CPPI Interrupt Enable Clear Register (TCPPIIENCLRR)964.21 Receive CPPI Control Register (RCPPICR)974.22 Receive CPPI Masked Status Register (RCPPIMSKSR)974.23 Receive CPPI Raw Status Register (RCPPIRAWSR)984.24 Receive CPPI Interrupt Enable Set Register (RCPPIENSETR)984.25 Receive CPPI Interrupt Enable Clear Register (RCPPIIENCLRR)994.26 Receive Buffer Count 0 Register (RBUFCNT0)994.27 Receive Buffer Count 1 Register (RBUFCNT1)1004.28 Receive Buffer Count 2 Register (RBUFCNT2)1004.29 Receive Buffer Count 3 Register (RBUFCNT3)1014.30 Transmit CPPI DMA State Word 0 (TCPPIDMASTATEW0)1014.31 Transmit CPPI DMA State Word 1 (TCPPIDMASTATEW1)1024.32 Transmit CPPI DMA State Word 2 (TCPPIDMASTATEW2)1024.33 Transmit CPPI DMA State Word 3 (TCPPIDMASTATEW3)1034.34 Transmit CPPI DMA State Word 4 (TCPPIDMASTATEW4)1034.35 Transmit CPPI DMA State Word 5 (TCPPIDMASTATEW5)1044.36 Transmit CPPI Completion Pointer (TCPPICOMPPTR)1044.37 Receive CPPI DMA State Word 0 (RCPPIDMASTATEW0)1054.38 Receive CPPI DMA State Word 1 (RCPPIDMASTATEW1)1054.39 Receive CPPI DMA State Word 2 (RCPPIDMASTATEW2)1074.40 Receive CPPI DMA State Word 3 (RCPPIDMASTATEW3)1074.41 Receive CPPI DMA State Word 4 (RCPPIDMASTATEW4)1094.42 Receive CPPI DMA State Word 5 (RCPPIDMASTATEW5)1094.43 Receive CPPI DMA State Word 6 (RCPPIDMASTATEW6)1104.44 Receive CPPI Completion Pointer (RCPPICOMPPTR)1104.45 Function Address Register (FADDR)1114.46 Power Management Register (POWER)1114.47 Interrupt Register for Endpoint 0 Plus Transmit Endpoints 1 to 4 (INTRTX)1124.48 Interrupt Register for Receive Endpoints 1 to 4 (INTRRX)1124.49 Interrupt Enable Register for INTRTX (INTRTXE)1134.50 Interrupt Enable Register for INTRRX (INTRRXE)1134.51 Interrupt Register for Common USB Interrupts (INTRUSB)1154.52 Interrupt Enable Register for INTRUSB (INTRUSBE)1164.53 Frame Number Register (FRAME)1174.54 Index Register for Selecting the Endpoint Status and Control Registers (INDEX)1174.55 Register to Enable the USB 2.0 Test Modes (TESTMODE)1184.56 Maximum Packet Size for Peripheral/Host Transmit Endpoint (TXMAXP)1194.57 Control Status Register for Endpoint 0 in Peripheral Mode (PERI_CSR0)1204.58 Control Status Register for Endpoint 0 in Host Mode (HOST_CSR0)1214.59 Control Status Register for Peripheral Transmit Endpoint (PERI_TXCSR)1224.60 Control Status Register for Host Transmit Endpoint (HOST_TXCSR)1234.61 Maximum Packet Size for Peripheral Host Receive Endpoint (RXMAXP)1244.62 Control Status Register for Peripheral Receive Endpoint (PERI_RXCSR)1254.63 Control Status Register for Host Receive Endpoint (HOST_RXCSR)1264.64 Count 0 Register (COUNT0)1284.65 Receive Count Register (RXCOUNT)1284.66 Type Register (Host mode only) (HOST_TYPE0)1294.67 Transmit Type Register (Host mode only) (HOST_TXTYPE)1294.68 NAKLimit0 Register (Host mode only) (HOST_NAKLIMIT0)1304.69 Transmit Interval Register (Host mode only) (HOST_TXINTERVAL)1304.70 Receive Type Register (Host mode only) (HOST_RXTYPE)1314.71 Receive Interval Register (Host mode only) (HOST_RXINTERVAL)1314.72 Configuration Data Register (CONFIGDATA)1324.73 Transmit and Receive FIFO Register for Endpoint 0 (FIFO0)1344.74 Transmit and Receive FIFO Register for Endpoint 1 (FIFO1)1354.75 Transmit and Receive FIFO Register for Endpoint 2 (FIFO2)1354.76 Transmit and Receive FIFO Register for Endpoint 3 (FIFO3)1364.77 Transmit and Receive FIFO Register for Endpoint 4 (FIFO4)1364.78 OTG Device Control Register (DEVCTL)1374.79 Transmit Endpoint FIFO Size (TXFIFOSZ)1384.80 Receive Endpoint FIFO Size (RXFIFOSZ)1384.81 Transmit Endpoint FIFO Address (TXFIFOADDR)1394.82 Receive Endpoint FIFO Address (RXFIFOADDR)1394.83 Transmit Function Address (TXFUNCADDR)1404.84 Transmit Hub Address (TXHUBADDR)1404.85 Transmit Hub Port (TXHUBPORT)1404.86 Receive Function Address (RXFUNCADDR)1414.87 Receive Hub Address (RXHUBADDR)1414.88 Receive Hub Port (RXHUBPORT)141Appendix A Revision History143Size: 1.06 MBPages: 144Language: EnglishOpen manual