SMSC LAN9311 User Manual

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

SMSC LAN9311/LAN9311i

161

Revision 1.4 (08-19-08)

 

The IEEE 1588 Clock/Events block is responsible for generating and controlling all IEEE 1588 clock
related events. A 64-bit comparator is included in this block which compares the 64-bit IEEE 1588 clock
wi t h   a   6 4 - b it   Cl o c k   Ta r g e t   l oa d e d   in   t h e  

  a n d  

.

When the IEEE 1588 clock equals the Clock Target, a clock event occurs which triggers the following:

„

The maskable interrupt 1588_TIMER_INT is set in the 

„

The RELOAD_ADD bit in the 

 is checked to determine 

the new Clock Target behavior:

–RELOAD_ADD = 1:

The new Clock Target is loaded from the 64-bit Reload / Add Registers (

).

–RELOAD_ADD = 0:

The Clock Target is incremented by the 

Writing the IEEE 1588 clock may cause the interrupt event to occur if the new IEEE 1588 clock
value is set equal to the current Clock Target.

The Clock Target reload function (RELOAD_ADD = 1) allows the host to pre-load the next trigger time.
The add function (RELOAD_ADD = 0), allows for a repeatable event. When the Clock Target overflows,
it will wrap around past 0, as will the 64-bit IEEE 1588 clock. Since the Clock Target and Reload / Add
Registers are 64-bits, they require two 32-bit write cycles, one to each half, before the registers are
affected. The writes may be in any order.

In addition to time stamping PTP packets, the IEEE 1588 clock value can be saved into a set of clock
capture registers based on the GPIO[9:8] inputs. When configured as outputs, GPIO[9:8] can be used
to output a signal based on an IEEE 1588 clock target compare event. Refer to 

 for information on using GPIO[9:8] for IEEE 1588 time

stamping functions.

The IEEE 1588 hardware time stamp unit provides multiple interrupt conditions. These include time
stamp indication on the transmitter and receiver side of each port, individual GPIO[9:8] input time
stamp interrupts, and a clock comparison event interrupt. All IEEE 1588 interrupts are located in the

 and are fully maskable via their

respective enable bits. Refer to 

 for bit-level definitions of all IEEE 1588 interrupts and enables.

All IEEE 1588 interrupts are ANDed with their individual enables and then ORed, as shown in

, generating the 1588_EVNT bit of the 

When configured as an input, GPIO[9:8] have the added functionality of clearing the Clock Target
interrupt bit (1588_TIMER_INT) of the 

on an active edge. GPIO inputs must be active for greater than 40 nS to be recognized as clear events.
For more information on IEEE 1588 GPIO interrupts, refer to 

Refer to 

 for additional information on the

LAN9311/LAN9311i interrupts.