SMSC LAN9311 User Manual

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

Revision 1.4 (08-19-08)

162

SMSC LAN9311/LAN9311i

 

This chapter details the LAN9311/LAN9311i General Purpose Timer (GPT) and the Free-Running
Clock.

The LAN9311/LAN9311i provides a 16-bit programmable General Purpose Timer that can be used to
generate periodic system interrupts. The resolution of this timer is 100uS.

The GPT loads the 

 with the value in the

GPT_LOAD field of the 

TIMER_EN bit of the 

 is asserted (1). On

a chip-level reset, or when the TIMER_EN bit changes from asserted (1) to de-asserted (0), the
GPT_LOAD field is initialized to FFFFh. The 

 is

also initialized to FFFFh on reset. Software can write a pre-load value into the GPT_LOAD field at any
time (e.g. before or after the TIMER_EN bit is asserted).

Once enabled, the GPT counts down until it reaches 0000h, or until a new pre-load value is written to
the GPT_LOAD field. At 0000h, the counter wraps around to FFFFh, asserts the GPT interrupt status
bit (GPT_INT) in the 

, asserts the IRQ interrupt (if GPT_INT_EN is

set in the 

), and continues counting. GPT_INT is a sticky bit. Once

this bit is asserted, it can only be cleared by writing a 1 to the bit. Refer to 

 for additional information on the GPT interrupt.

The Free-Running Clock (FRC) is a simple 32-bit up-counter that operates from a fixed 25MHz clock.
The current FRC value can be read via the 

. On

assertion of a chip-level reset, this counter is cleared to zero. On de-assertion of a reset, the counter
is incremented once for every 25MHz clock cycle. When the maximum count has been reached, the
counter rolls over to zeros. The FRC does not generate interrupts.

The free running counter can take up to 160nS to clear after a reset event.