SMSC LAN9311 User Manual

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

SMSC LAN9311/LAN9311i

237

Revision 1.4 (08-19-08)

 

This read/write register is used in conjunction with the 

 to control the read and write operations to the various Switch Fabric CSR’s.

Refer to 

 for details on the

registers indirectly accessible via this register.

Offset:

1B0h

Size:

32 bits

31

CSR Busy (CSR_BUSY)
When a 1 is written to this bit, the read or write operation (as determined by 
the R_nW bit) is performed to the specified Switch Fabric CSR in 

. This bit will remain set until the operation is 

complete, at which time the bit will clear. In the case of a read, the clearing 
of this bit indicates to the Host that valid data can be read from the 

. The 

SWITCH_CSR_CMD and SWITCH_CSR_DATA registers should not be 
modified until this bit is cleared.

R/W

SC

0b

30

Read/Write (R_nW)
This bit determines whether a read or write operation is performed by the 
Host to the specified Switch Engine CSR.

R/W

0b

29

Auto Increment (AUTO_INC)
This bit enables/disables the auto increment feature.

When this bit is set, a write to the 

 register will automatically set the 

 bit. Once the write command is finished, the 

 will automatically increment. 

When this bit is set, a read from the 

 will automatically increment the 

 and set the 

 bit. This 

bit should be cleared by software before the last read from the 
SWITCH_CSR_DATA register.

This bit has precedence over the 

 bit

R/W

0b

28

Auto Decrement (AUTO_DEC)
This bit enables/disables the auto decrement feature.

When this bit is set, a write to the 

 will automatically set the 

 

bit. Once the write command is finished, the 

 will automatically decrement. 

When this bit is set, a read from the 

 will automatically decrement the 

 and set the 

 bit. This 

bit should be cleared by software before the last read from the 
SWITCH_CSR_DATA register.

R/W

0b

27:20

RO

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