SMSC LAN9311 User Manual

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

SMSC LAN9311/LAN9311i

239

Revision 1.4 (08-19-08)

 

This register contains the upper 16-bits of the MAC address used by the switch for Pause frames. This
r e g i s t e r   i s   u s e d   i n   c o n j u n c t i o n   w i t h  

. The contents of this register are optionally loaded from the EEPROM at

power-on through the EEPROM Loader if a programmed EEPROM is detected. The least significant
byte of this register (bits [7:0]) is loaded from address 05h of the EEPROM. The second byte (bits
[15:8]) is loaded from address 06h of the EEPROM. These EEPROM values are also loaded into the

. The Host can update the contents of this field

after the initialization process has completed.

 for details on how the EEPROM Loader loads

this register.  

 contains additional details on using the

EEPROM Loader.

Offset:

1F0h

Size:

32 bits

31:16

RO

-

15:0

Physical Address[47:32]
This field contains the upper 16-bits (47:32) of the physical address of the 
Switch Fabric MACs.

R/W

FFFFh