SMSC LAN9311 User Manual

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

SMSC LAN9311/LAN9311i

287

Revision 1.4 (08-19-08)

 

This section details the various LAN9311/LAN9311i Ethernet PHY control and status registers. The
LAN9311/LAN9311i contains three PHY’s: Port 1 PHY, Port 2 PHY and a Virtual PHY. All PHY registers
follow the IEEE 802.3 (clause 22.2.4) specified MII management register set. All functionality and bit
definitions comply with these standards. The IEEE 802.3 specified register index (in decimal) is
included with each register definition, allowing for addressing of these registers via the MII serial
management protocol. For additional information on the MII management protocol, refer to the IEEE
802.3 Specification.

Each individual PHY is assigned a unique PHY address as detailed in 

The Virtual PHY provides a basic MII management interface for communication with the Host MAC for
connection to the Host as if it was attached to a single port PHY. The Virtual PHY registers differ from
the Port 1 & 2 PHY registers in that they are addressable via the memory map, as described in

, as well as serially. These modes of access are described in 

Because the Virtual PHY registers are also memory mapped, their definitions have been included in
the 

. A list of the Virtual

PHY MII addressable registers and their corresponding register index numbers is also included in

.

When serially accessed, the Virtual PHY registers are only 16-bits wide, as is standard for MII
management of PHY’s.

The Port 1 and Port 2 PHY’s are comparable in functionality and have an identical set of non-memory
mapped registers. The Port 1 and Port 2 PHY registers are not memory mapped. These registers are
indirectly accessed through the 

 and 

 registers in the Host MAC via the MII serial management protocol

specified in IEEE 802.3 clause 22. Because the Port 1 & 2 PHY registers are functionally identical,
their register descriptions have been consolidated. A lowercase “x” has been appended to the end of
each PHY register name in this section, where “x” should be replaced with “1” or “2” for the Port 1
PHY or the Port 2 PHY registers respectively. A list of the Port 1 & 2 PHY MII addressable registers
and their corresponding register index numbers is included in 

. Each individual PHY is

assigned a unique PHY address as detailed in 

.

0

PHY_BASIC_CONTROL_x

Port x PHY Basic Control Register, 

1

PHY_BASIC_STATUS_x

Port x PHY Basic Status Register, 

2

PHY_ID_MSB_x

Port x PHY Identification MSB Register, 

3

PHY_ID_LSB_x

Port x PHY Identification LSB Register, 

4

PHY_AN_ADV_x

Port x PHY Auto-Negotiation Advertisement Register, 

5

PHY_AN_LP_BASE_ABILITY_x

Port x PHY Auto-Negotiation Link Partner Base Page Ability 
Register, 

6

PHY_AN_EXP_x

Port x PHY Auto-Negotiation Expansion Register,