Intel S5000XAL User Manual

 

This section will describe the general functionality of the memory controller hub as it is implemented on 
this server board. Depending on the version of the server board in use, it may support either the Intel

®

 

5000P MCH or the Intel

®

 5000X MCH. Features that are unique to a particular MCH will be so referenced. 

The Memory Controller Hub (MCH) is a single 1432 pin FCBGA package which includes the following 
core platform functions: 

•  System Bus Interface for the processor sub-system  
• Memory 

Controller 

•  PCI Express* Ports including the Enterprise South Bridge Interface (ESI) 
•  FBD Thermal Management 
• SMBUS 

Interface 

Additional information about MCH functionality can be obtained from the Intel

 the Intel

 Yellow Cover documents can only be obtained under NDA with Intel and ordered through an Intel 

representative. 

The MCH is configured for symmetric multi-processing across two independent front side bus interfaces 
that connect to the Dual-Core Intel

®

 Xeon

®

 processors 5000 sequence. Each front side bus on the MCH 

uses a 64-bit wide 1066 or 1333 MHz data bus. The 1333 MHz data bus is capable of transferring data at 
up to 10.66 GB/s. The MCH supports a 36-bit wide address bus, capable of addressing up to 64 GB of 
memory. The MCH is the priority agent for both front side bus interfaces, and is optimized for one 
processor on each bus.  

The server board supports one or two Dual-Core Intel

®

 Xeon

®

 processors 5000 sequence, with system 

bus speeds of 667 MHz, 1066 MHz, and1333 MHz, and core frequencies starting at 2.67 GHz. Previous 
generations of the Intel

®

 Xeon

®

 processor are not supported on this server board.  

 Only Dual-Core Intel

®

 Xeon

®

 processors 5000 sequence, that support system bus speeds of 667 

MHz, 1066 MHz, and1333 MHz are supported on this server board. See the following table for a list of 
supported processors.