Intel 8XC251SQ User Manual
10-7
SERIAL I/O PORT
10.3 FRAMING BIT ERROR DETECTION (MODES 1, 2, AND 3)
Framing bit error detection is provided for the three asynchronous modes. To enable the framing
bit error detection feature, set the SMOD0 bit in the PCON register (Figure 12-1 on page 12-2).
When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit.
An invalid stop bit may result from noise on the serial lines or from simultaneous transmission
by two CPUs. If a valid stop bit is not found, the software sets the FE bit in the SCON register
(Figure 10-2).
bit error detection feature, set the SMOD0 bit in the PCON register (Figure 12-1 on page 12-2).
When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit.
An invalid stop bit may result from noise on the serial lines or from simultaneous transmission
by two CPUs. If a valid stop bit is not found, the software sets the FE bit in the SCON register
(Figure 10-2).
Software may examine the FE bit after each reception to check for data errors. Once set, only soft-
ware or a reset can clear the FE bit. Subsequently received frames with valid stop bits cannot clear
the FE bit.
ware or a reset can clear the FE bit. Subsequently received frames with valid stop bits cannot clear
the FE bit.
10.4 MULTIPROCESSOR COMMUNICATION (MODES 2 AND 3)
Modes 2 and 3 provide a ninth-bit mode to facilitate multiprocessor communication. To enable
this feature, set the SM2 bit in the SCON register (Figure 10-2). When the multiprocessor com-
munication feature is enabled, the serial port can differentiate between data frames (ninth bit
clear) and address frames (ninth bit set). This allows the microcontroller to function as a slave
processor in an environment where multiple slave processors share a single serial line.
this feature, set the SM2 bit in the SCON register (Figure 10-2). When the multiprocessor com-
munication feature is enabled, the serial port can differentiate between data frames (ninth bit
clear) and address frames (ninth bit set). This allows the microcontroller to function as a slave
processor in an environment where multiple slave processors share a single serial line.
When the multiprocessor communication feature is enabled, the receiver ignores frames with the
ninth bit clear. The receiver examines frames with the ninth bit set for an address match. If the
received address matches the slave’s address, the receiver hardware sets the RB8 bit and the RI
bit in the SCON register, generating an interrupt.
ninth bit clear. The receiver examines frames with the ninth bit set for an address match. If the
received address matches the slave’s address, the receiver hardware sets the RB8 bit and the RI
bit in the SCON register, generating an interrupt.
NOTE
The ES bit must be set in the IE register to allow the RI bit to generate an
interrupt. The IE register is described in Chapter 8, Interrupts.
interrupt. The IE register is described in Chapter 8, Interrupts.
The addressed slave’s software then clears the SM2 bit in the SCON register and prepares to re-
ceive the data bytes. The other slaves are unaffected by these data bytes because they are waiting
to respond to their own addresses.
ceive the data bytes. The other slaves are unaffected by these data bytes because they are waiting
to respond to their own addresses.
10.5 AUTOMATIC ADDRESS RECOGNITION
The automatic address recognition feature is enabled when the multiprocessor communication
feature is enabled (i.e., the SM2 bit is set in the SCON register).
feature is enabled (i.e., the SM2 bit is set in the SCON register).