Intel 8XC251SQ User Manuals

Table of Contents

• 8XC251SA, 8XC251SB, 8XC251SP, 8XC251SQ Embedded Microcontroller User’s Manual

  3
  • CONTENTS

    5
  • CHAPTER 1 Guide to this Manual

    21
    • 1.1 Manual Contents

      21
    • 1.2 Notational Conventions and Terminology

      23
    • 1.3 Related Documents

      25
      • 1.3.1 Data Sheet

        26
      • 1.3.2 Application Notes

        26
    • 1.4 Application Support Services

      27
      • 1.4.1 World Wide Web

        27
      • 1.4.2 CompuServe Forums

        27
      • 1.4.3 FaxBack Service

        28
      • 1.4.4 Bulletin Board System (BBS)

        28
  • CHAPTER 2 Architectural Overview

    33
    • 2.1 8XC251SA, SB, SP, SQ Architecture

      35
    • 2.2 MCS 251 Microcontroller Core

      36
      • 2.2.1 CPU

        37
      • 2.2.2 Clock and Reset Unit

        38
      • 2.2.3 Interrupt Handler

        39
      • 2.2.4 On-chip Code Memory

        39
      • 2.2.5 On-chip RAM

        39
    • 2.3 On-chip Peripherals

      39
      • 2.3.1 Timer/Counters and Watchdog Timer

        39
      • 2.3.2 Programmable Counter Array (PCA)

        40
      • 2.3.3 Serial I/O Port

        40
  • CHAPTER 3 Address Spaces

    43
    • 3.1 Address Spaces for MCS® 251 Microcontrollers

      43
      • 3.1.1 Compatibility with the MCS® 51 Architecture

        44
    • 3.2 8XC251SA, SB, SP, SQ Memory Space

      47
      • 3.2.1 On-chip General-purpose Data RAM

        50
      • 3.2.2 On-chip Code Memory (83C251SA, SB, SP, SQ/87...

        50
        • 3.2.2.1 Accessing On-chip Code Memory in Region 00...

          51
      • 3.2.3 External Memory

        52
    • 3.3 8XC251SA, SB, SP, SQ Register File

      52
      • 3.3.1 Byte, Word, and Dword Registers

        55
      • 3.3.2 Dedicated Registers

        55
        • 3.3.2.1 Accumulator and B Register

          55
        • 3.3.2.2 Extended Data Pointer, DPX

          56
        • 3.3.2.3 Extended Stack Pointer, SPX

          57
    • 3.4 Special Function Registers (SFRs)

      58
  • CHAPTER 4 Device Configuration

    65
    • 4.1 Configuration Overview

      65
    • 4.2 Device Configuration

      65
    • 4.3 The Configuration Bits

      68
    • 4.4 Configuration Byte Location Selector (UCON)

      69
    • 4.5 Configuring the External Memory Interface

      72
      • 4.5.1 Page Mode and Nonpage Mode (PAGE#)

        72
      • 4.5.2 Configuration Bits RD1:0

        73
        • 4.5.2.1 RD1:0 = 00 (18 External Address Bits)

          73
        • 4.5.2.2 RD1:0 = 01 (17 External Address Bits)

          73
        • 4.5.2.3 RD1:0 = 10 (16 External Address Bits)

          76
        • 4.5.2.4 RD1:0 = 11 (Compatible with MCS 51 Microco...

          76
      • 4.5.3 Wait State Configuration Bits

        76
        • 4.5.3.1 Configuration Bits WSA1:0#, WSB1:#

          76
        • 4.5.3.2 Configuration Bit WSB

          76
        • 4.5.3.3 Configuration Bit XALE#

          77
    • 4.6 Opcode Configurations (SRC)

      77
      • 4.6.1 Selecting Binary Mode or Source Mode

        78
    • 4.7 Mapping On-chip Code Memory to Data Memory (EM...

      80
    • 4.8 Interrupt Mode (INTR)

      80
  • CHAPTER 5 Programming

    83
    • 5.1 Source Mode or Binary Mode Opcodes

      83
    • 5.2 Programming Features of the MCS® 251 Architect...

      83
      • 5.2.1 Data Types

        84
        • 5.2.1.1 Order of Byte Storage for Words and Double...

          84
      • 5.2.2 Register Notation

        84
      • 5.2.3 Address Notation

        84
      • 5.2.4 Addressing Modes

        86
    • 5.3 Data Instructions

      86
      • 5.3.1 Data Addressing Modes

        86
        • 5.3.1.1 Register Addressing

          87
        • 5.3.1.2 Immediate

          87
        • 5.3.1.3 Direct

          87
        • 5.3.1.4 Indirect

          88
        • 5.3.1.5 Displacement

          90
      • 5.3.2 Arithmetic Instructions

        90
      • 5.3.3 Logical Instructions

        91
      • 5.3.4 Data Transfer Instructions

        92
    • 5.4 Bit Instructions

      93
      • 5.4.1 Bit Addressing

        93
    • 5.5 Control Instructions

      94
      • 5.5.1 Addressing Modes for Control Instructions

        95
      • 5.5.2 Conditional Jumps

        96
      • 5.5.3 Unconditional Jumps

        97
      • 5.5.4 Calls and Returns

        97
    • 5.6 Program Status Words

      98
  • CHAPTER 6 Interrupt System

    105
    • 6.1 OVERVIEW

      105
    • 6.2 8XC251SA, SB, SP, SQ Interrupt Sources

      107
      • 6.2.1 External Interrupts

        107
      • 6.2.2 Timer Interrupts

        108
    • 6.3 Programmable Counter Array (PCA) Interrupt

      109
    • 6.4 SERIAL POrt Interrupt

      109
    • 6.5 Interrupt Enable

      109
    • 6.6 Interrupt Priorities

      111
    • 6.7 Interrupt Processing

      113
      • 6.7.1 Minimum Fixed Interrupt Time

        114
      • 6.7.2 Variable Interrupt Parameters

        114
        • 6.7.2.1 Response Time Variables

          114
        • 6.7.2.2 Computation of Worst-case Latency With Var...

          116
        • 6.7.2.3 Latency Calculations

          117
        • 6.7.2.4 Blocking Conditions

          118
        • 6.7.2.5 Interrupt Vector Cycle

          118
      • 6.7.3 ISRs in Process

        119
  • CHAPTER 7 Input/Output Ports

    123
    • 7.1 Input/Output port overview

      123
    • 7.2 I/O Configurations

      124
    • 7.3 Port 1 and Port 3

      124
    • 7.4 Port 0 and Port 2

      124
    • 7.5 Read-Modify-Write Instructions

      127
    • 7.6 Quasi-bidirectional Port Operation

      128
    • 7.7 Port Loading

      129
    • 7.8 External Memory Access

      129
  • CHAPTER 8 Timer/Counters and WatchDog Timer

    135
    • 8.1 Timer/Counter Overview

      135
    • 8.2 Timer/Counter Operation

      135
    • 8.3 Timer 0

      137
      • 8.3.1 Mode 0 (13-bit Timer)

        138
      • 8.3.2 Mode 1 (16-bit Timer)

        138
      • 8.3.3 Mode 2 (8-bit Timer With Auto-reload)

        139
      • 8.3.4 Mode 3 (Two 8-bit Timers)

        139
    • 8.4 Timer 1

      139
      • 8.4.1 Mode 0 (13-bit Timer)

        143
      • 8.4.2 Mode 1 (16-bit Timer)

        143
      • 8.4.3 Mode 2 (8-bit Timer with Auto-reload)

        143
      • 8.4.4 Mode 3 (Halt)

        143
    • 8.5 Timer 0/1 Applications

      143
      • 8.5.1 Auto-load Setup Example

        143
      • 8.5.2 Pulse Width Measurements

        144
    • 8.6 Timer 2

      144
      • 8.6.1 Capture Mode

        145
      • 8.6.2 Auto-reload Mode

        146
        • 8.6.2.1 Up Counter Operation

          146
        • 8.6.2.2 Up/Down Counter Operation

          147
      • 8.6.3 Baud Rate Generator Mode

        148
      • 8.6.4 Clock-out Mode

        148
    • 8.7 Watchdog Timer

      150
      • 8.7.1 Description

        150
      • 8.7.2 Using the WDT

        152
      • 8.7.3 WDT During Idle Mode

        152
      • 8.7.4 WDT During PowerDown

        152
  • CHAPTER 9 Programmable Counter Array

    155
    • 9.1 PCA Description

      155
      • 9.1.1 Alternate Port Usage

        156
    • 9.2 PCA Timer/Counter

      156
    • 9.3 PCA Compare/Capture Modules

      159
      • 9.3.1 16-bit Capture Mode

        159
      • 9.3.2 Compare Modes

        161
      • 9.3.3 16-bit Software Timer Mode

        161
      • 9.3.4 High-speed Output Mode

        162
      • 9.3.5 PCA Watchdog Timer Mode

        163
      • 9.3.6 Pulse Width Modulation Mode

        165
  • CHAPTER 10 Serial I/O Port

    173
    • 10.1 Overview

      173
    • 10.2 Modes of Operation

      176
      • 10.2.1 Synchronous Mode (Mode 0)

        176
        • 10.2.1.1 Transmission (Mode 0)

          176
        • 10.2.1.2 Reception (Mode 0)

          177
      • 10.2.2 Asynchronous Modes (Modes 1, 2, and 3)

        178
        • 10.2.2.1 Transmission (Modes 1, 2, 3)

          178
        • 10.2.2.2 Reception (Modes 1, 2, 3)

          178
    • 10.3 Framing Bit Error Detection (Modes 1, 2, and ...

      179
    • 10.4 Multiprocessor Communication (Modes 2 and 3)

      179
    • 10.5 Automatic Address Recognition

      179
      • 10.5.1 Given Address

        180
      • 10.5.2 Broadcast Address

        181
      • 10.5.3 Reset Addresses

        182
    • 10.6 Baud Rates

      182
      • 10.6.1 Baud Rate for Mode 0

        182
      • 10.6.2 Baud Rates for Mode 2

        182
      • 10.6.3 Baud Rates for Modes 1 and 3

        182
        • 10.6.3.1 Timer 1 Generated Baud Rates (Modes 1 and...

          183
        • 10.6.3.2 Selecting Timer 1 as the Baud Rate Genera...

          183
        • 10.6.3.3 Timer 2 Generated Baud Rates (Modes 1 and...

          184
        • 10.6.3.4 Selecting Timer 2 as the Baud Rate Genera...

          184
  • CHAPTER 11 Minimum Hardware Setup

    189
    • 11.1 Minimum Hardware Setup

      189
    • 11.2 Electrical Environment

      190
      • 11.2.1 Power and Ground Pins

        190
      • 11.2.2 Unused Pins

        190
      • 11.2.3 Noise Considerations

        190
    • 11.3 Clock Sources

      191
      • 11.3.1 On-chip Oscillator (Crystal)

        191
      • 11.3.2 On-chip Oscillator (Ceramic Resonator)

        192
      • 11.3.3 External Clock

        192
    • 11.4 Reset

      193
      • 11.4.1 Externally Initiated Resets

        194
      • 11.4.2 WDT Initiated Resets

        194
      • 11.4.3 Reset Operation

        194
      • 11.4.4 Power-on Reset

        195
  • CHAPTER 12 Special Operating Modes

    199
    • 12.1 General

      199
    • 12.2 Power Control Register

      199
      • 12.2.1 Serial I/O Control Bits

        199
      • 12.2.2 Power Off Flag

        199
    • 12.3 Idle Mode

      202
      • 12.3.1 Entering Idle Mode

        202
      • 12.3.2 Exiting Idle Mode

        203
    • 12.4 Powerdown Mode

      203
      • 12.4.1 Entering Powerdown Mode

        204
      • 12.4.2 Exiting Powerdown Mode

        204
    • 12.5 ON-Circuit emulation (Once) Mode

      205
      • 12.5.1 Entering ONCE Mode

        205
      • 12.5.2 Exiting ONCE Mode

        205
  • CHAPTER 13 External Memory Interface

    209
    • 13.1 Overview

      209
    • 13.2 External Bus Cycles

      211
      • 13.2.1 Bus Cycle Definitions

        211
      • 13.2.2 Nonpage Mode Bus Cycles

        212
      • 13.2.3 Page Mode Bus Cycles

        213
    • 13.3 Wait States

      216
    • 13.4 External Bus Cycles with Configurable Wait St...

      216
      • 13.4.1 Extending RD#/WR#/PSEN#

        216
      • 13.4.2 Extending ALE

        218
    • 13.5 External Bus Cycles with Real-time Wait State...

      218
      • 13.5.1 Real-time WAIT# Enable (RTWE)

        220
      • 13.5.2 Real-time WAIT CLOCK Enable (RTWCE)

        220
      • 13.5.3 Real-time Wait State Bus Cycle Diagrams

        220
    • 13.6 Configuration Byte Bus Cycles

      223
    • 13.7 Port 0 and Port 2 Status

      224
      • 13.7.1 Port 0 and Port 2 Pin Status in Nonpage Mod...

        224
      • 13.7.2 Port 0 and Port 2 Pin Status in Page Mode

        225
    • 13.8 External Memory Design Examples

      226
      • 13.8.1 Example 1: RD1:0 = 00, 18-bit Bus, External...

        226
      • 13.8.2 Example 2: RD1:0 = 01, 17-bit Bus, External...

        228
      • 13.8.3 Example 3: RD1:0 = 01, 17-bit Bus, External...

        230
      • 13.8.4 Example 4: RD1:0 = 10, 16-bit Bus, External...

        232
      • 13.8.5 Example 5: RD1:0 = 11, 16-bit Bus, External...

        234
        • 13.8.5.1 An Application Requiring Fast Access to t...

          234
        • 13.8.5.2 An Application Requiring Fast Access to D...

          234
      • 13.8.6 Example 6: RD1:0 = 11, 16-bit Bus, External...

        237
      • 13.8.7 Example 7: RD1:0 = 01, 17-bit Bus, External...

        238
  • CHAPTER 14 Programming and Verifying Nonvolatile M...

    241
    • 14.1 General

      241
      • 14.1.1 Programming Considerations for On-chip Code...

        242
      • 14.1.2 EPROM Devices

        243
    • 14.2 Programming and Verifying Modes

      243
    • 14.3 General Setup

      243
    • 14.4 Programming Algorithm

      245
    • 14.5 Verify Algorithm

      246
    • 14.6 Programmable Functions

      246
      • 14.6.1 On-chip Code Memory

        247
      • 14.6.2 Configuration Bytes

        247
      • 14.6.3 Lock Bit System

        247
      • 14.6.4 Encryption Array

        248
      • 14.6.5 Signature Bytes

        248
    • 14.7 Verifying the 83C251SA, SB, SP, SQ (ROM)

      249
  • APPENDIX A Instruction Set Reference

    253
    • A.1 Notation for instruction Operands

      254
    • A.2 Opcode Map and Supporting Tables

      256
    • A.3 Instruction Set Summary

      263
      • A.3.1 Execution Times for Instructions that Access...

        263
      • A.3.2 Instruction Summaries     

        266
    • A.4 Instruction Descriptions

      278
  • APPENDIX B Signal Descriptions

    393
  • APPENDIX C Registers

    403
  • GLOSSARY

    439
  • INDEX

    449
• FIGURES

  34
  • Figure 21. Functional Block Diagram of the 8XC251...

    34
  • Figure 22. The CPU

    37
  • Figure 23. Clocking Definitions

    38
  • Figure 31. Address Spaces for MCS® 251 Microcontr...

    43
  • Figure 32. Address Spaces for the MCS® 51 Archite...

    45
  • Figure 33. Address Space Mappings MCS® 51 Archite...

    46
  • Figure 34. 8XC251SA, SB, SP, SQ Address Space

    48
  • Figure 35. Hardware Implementation of the 8XC251S...

    49
  • Figure 36. The Register File

    53
  • Figure 37. Register File Locations 0–7

    54
  • Figure 38. Dedicated Registers in the Register Fi...

    56
  • Figure 41. Configuration Array (On-chip)

    66
  • Figure 42. Configuration Array (External)

    67
  • Figure 43. Configuration Byte UCONFIG0

    70
  • Figure 44. Configuration Byte UCONFIG1

    71
  • Figure 45. Internal/External Address Mapping (RD1...

    74
  • Figure 46. Internal/External Address Mapping (RD1...

    75
  • Figure 47. Binary Mode Opcode Map

    79
  • Figure 48. Source Mode Opcode Map

    79
  • Figure 51. Word and Double-word Storage in Big En...

    85
  • Figure 52. Program Status Word Register

    100
  • Figure 53. Program Status Word 1 Register

    101
  • Figure 61. Interrupt Control System

    106
  • Figure 62. Interrupt Enable Register

    110
  • Figure 63. Interrupt Priority High Register

    112
  • Figure 64. Interrupt Priority Low Register

    112
  • Figure 65. The Interrupt Process

    113
  • Figure 66. Response Time Example #1

    115
  • Figure 67. Response Time Example #2

    116
  • Figure 71. Port 1 and Port 3 Structure

    125
  • Figure 72. Port 0 Structure

    125
  • Figure 73. Port 2 Structure

    126
  • Figure 74. Internal Pullup Configurations

    129
  • Figure 81. Basic Logic of the Timer/Counters

    136
  • Figure 82. Timer 0/1 in Mode 0 and Mode 1

    138
  • Figure 83. Timer 0/1 in Mode 2, Auto-Reload

    139
  • Figure 84. Timer 0 in Mode 3, Two 8-bit Timers

    140
  • Figure 85. TMOD: Timer/Counter Mode Control Regis...

    141
  • Figure 86. TCON: Timer/Counter Control Register

    142
  • Figure 87. Timer 2: Capture Mode

    145
  • Figure 88. Timer 2: Auto Reload Mode (DCEN = 0)

    146
  • Figure 89. Timer 2: Auto Reload Mode (DCEN = 1)

    147
  • Figure 810. Timer 2: Clock Out Mode

    149
  • Figure 811. T2MOD: Timer 2 Mode Control Register

    150
  • Figure 812. T2CON: Timer 2 Control Register

    151
  • Figure 91. Programmable Counter Array

    157
  • Figure 92. PCA 16-bit Capture Mode

    160
  • Figure 93. PCA Software Timer and High-speed Outp...

    162
  • Figure 94. PCA Watchdog Timer Mode

    164
  • Figure 95. PCA 8-bit PWM Mode

    165
  • Figure 96. PWM Variable Duty Cycle

    166
  • Figure 97. CMOD: PCA Timer/Counter Mode Register

    167
  • Figure 98. CCON: PCA Timer/Counter Control Regist...

    168
  • Figure 99. CCAPMx: PCA Compare/Capture Module Mod...

    169
  • Figure 101. Serial Port Block Diagram

    174
  • Figure 102. SCON: Serial Port Control Register

    175
  • Figure 103. Mode 0 Timing

    177
  • Figure 104. Data Frame (Modes 1, 2, and 3) 

    178
  • Figure 105. Timer 2 in Baud Rate Generator Mode

    185
  • Figure 111. Minimum Setup

    189
  • Figure 112. CHMOS On-chip Oscillator

    191
  • Figure 113. External Clock Connection

    192
  • Figure 114. External Clock Drive Waveforms

    193
  • Figure 115. Reset Timing Sequence

    196
  • Figure 121. Power Control (PCON) Register

    200
  • Figure 122. Idle and Powerdown Clock Control

    201
  • Figure 131. Bus Structure in Nonpage Mode and Pag...

    209
  • Figure 132. External Code Fetch (Nonpage Mode)

    212
  • Figure 133. External Data Read (Nonpage Mode)

    212
  • Figure 134. External Data Write (Nonpage Mode)

    213
  • Figure 135. External Code Fetch (Page Mode)

    214
  • Figure 136. External Data Read (Page Mode)

    215
  • Figure 137. External Data Write (Page Mode)

    215
  • Figure 138. External Code Fetch (Nonpage Mode, On...

    217
  • Figure 139. External Data Write (Nonpage Mode, On...

    217
  • Figure 1310. External Code Fetch (Nonpage Mode, O...

    218
  • Figure 1311. Real-time Wait State Control Registe...

    219
  • Figure 1312. External Code Fetch/Data Read (Nonpa...

    221
  • Figure 1313. External Data Write (Nonpage Mode, R...

    221
  • Figure 1314. External Data Read (Page Mode, RT Wa...

    222
  • Figure 1315. External Data Write (Page Mode, RT W...

    222
  • Figure 1316. Configuration Byte Bus Cycles

    223
  • Figure 1317. Bus Diagram for Example 1: 80C251SB ...

    226
  • Figure 1318. Address Space for Example 1

    227
  • Figure 1319. Bus Diagram for Example 2: 80C251SB ...

    228
  • Figure 1320. Address Space for Example 2

    229
  • Figure 1321. Bus Diagram for Example 3: 87C251SB/...

    230
  • Figure 1322. Address Space for Example 3

    231
  • Figure 1323. Bus Diagram for Example 4: 87C251SB/...

    232
  • Figure 1324. Address Space for Example 4

    233
  • Figure 1325. Bus Diagram for Example 5: 80C251SB ...

    235
  • Figure 1326. Address Space for Examples 5 and 6

    236
  • Figure 1327. Bus Diagram for Example 6: 80C251SB ...

    237
  • Figure 1328. Bus Diagram for Example 7: 80C251SB ...

    238
  • Figure 141. Setup for Programming and Verifying N...

    245
  • Figure 142. Program/Verify Bus Cycles

    246
  • Figure B1. 8XC251SA, SB, SP, SQ 44-pin PLCC Packa...

    393
  • Figure B2. 8XC251SA, SB, SP, SQ 40-pin PDIP and C...

    395
• TABLES

  27
  • Table 11. Intel Application Support Services

    27
  • Table 21. 8XC251SA, SB, SP, SQ Features

    35
  • Table 31. Address Mappings

    46
  • Table 32. Minimum Times to Fetch Two Bytes of Cod...

    51
  • Table 33. Register Bank Selection

    54
  • Table 34. Dedicated Registers in the Register Fil...

    57
  • Table 35. 8XC251SA, SB, SP, SQ SFR Map and Reset ...

    59
  • Table 36. Core SFRs

    60
  • Table 37. I/O Port SFRs

    60
  • Table 38. Serial I/O SFRs

    61
  • Table 39. Timer/Counter and Watchdog Timer SFRs

    61
  • Table 310. Programmable Counter Array (PCA) SFRs...

    61
  • Table 41. External Addresses for Configuration Ar...

    68
  • Table 42. Memory Signal Selections (RD1:0)

    72
  • Table 43. RD#, WR#, PSEN# External Wait States

    77
  • Table 44. Examples of Opcodes in Binary and Sourc...

    78
  • Table 51. Data Types

    84
  • Table 52. Notation for Byte Registers, Word Regis...

    85
  • Table 53. Addressing Modes for Data Instructions ...

    88
  • Table 54. Addressing Modes for Data Instructions ...

    89
  • Table 55. Bit-addressable Locations

    93
  • Table 56. Addressing Two Sample Bits

    94
  • Table 57. Addressing Modes for Bit Instructions

    94
  • Table 58. Addressing Modes for Control Instructio...

    95
  • Table 59. Compare-conditional Jump Instructions

    96
  • Table 510. The Effects of Instructions on the PSW...

    99
  • Table 61. Interrupt System Pin Signals

    105
  • Table 62. Interrupt System Special Function Regis...

    107
  • Table 63. Interrupt Control Matrix

    108
  • Table 64. Level of Priority

    111
  • Table 65. Interrupt Priority Within Level

    111
  • Table 66. Interrupt Latency Variables

    117
  • Table 67. Actual vs. Predicted Latency Calculatio...

    117
  • Table 71. Input/Output Port Pin Descriptions 

    123
  • Table 72. Instructions for External Data Moves

    131
  • Table 81. Timer/Counter and Watchdog Timer SFRs

    136
  • Table 82. External Signals

    137
  • Table 83. Timer 2 Modes of Operation

    149
  • Table 91. PCA Special Function Registers (SFRs)

    158
  • Table 92. External Signals

    158
  • Table 93. PCA Module Modes

    168
  • Table 101. Serial Port Signals

    173
  • Table 102. Serial Port Special Function Registers...

    174
  • Table 103. Summary of Baud Rates

    182
  • Table 104. Timer 1 Generated Baud Rates for Seria...

    184
  • Table 105. Selecting the Baud Rate Generator(s)

    185
  • Table 106. Timer 2 Generated Baud Rates

    186
  • Table 121. Pin Conditions in Various Modes

    201
  • Table 131. External Memory Interface Signals

    210
  • Table 132. Bus Cycle Definitions (No Wait States)...

    211
  • Table 133. Port 0 and Port 2 Pin Status In Normal...

    224
  • Table 141. Programming and Verifying Modes 

    244
  • Table 142. Lock Bit Function

    248
  • Table 143. Contents of the Signature Bytes

    249
  • Table A1. Notation for Register Operands

    254
  • Table A2. Notation for Direct Addresses

    255
  • Table A3. Notation for Immediate Addressing

    255
  • Table A4. Notation for Bit Addressing

    255
  • Table A5. Notation for Destinations in Control In...

    255
  • Table A6. Instructions for MCS® 51 Microcontrolle...

    256
  • Table A7. New Instructions for the MCS® 251 Archi...

    257
  • Table A8. Data Instructions

    258
  • Table A9. High Nibble, Byte 0 of Data Instruction...

    258
  • Table A10. Bit Instructions

    259
  • Table A11. Byte 1 (High Nibble) for Bit Instructi...

    259
  • Table A12. PUSH/POP Instructions

    260
  • Table A13. Control Instructions

    260
  • Table A14. Displacement/Extended MOVs

    261
  • Table A15. INC/DEC

    262
  • Table A16. Encoding for INC/DEC

    262
  • Table A17. Shifts

    262
  • Table A18. State Times to Access the Port SFRs(C...

    264
  • Table A19. Summary of Add and Subtract Instructio...

    266
  • Table A20. Summary of Compare Instructions

    267
  • Table A21. Summary of Increment and Decrement Ins...

    268
  • Table A22. Summary of Multiply, Divide, and Decim...

    268
  • Table A23. Summary of Logical Instructions (Conti...

    269
  • Table A24. Summary of Move Instructions (Continue...

    271
  • Table A25. Summary of Exchange, Push, and Pop Ins...

    274
  • Table A26. Summary of Bit Instructions 

    275
  • Table A27. Summary of Control Instructions (Conti...

    276
  • Table A28. Flag Symbols

    278
  • Table B1. PLCC/DIP Pin Assignments Listed by Func...

    394
  • Table B2. Signal Descriptions (Continued)

    395
  • Table B3. Memory Signal Selections (RD1:0)

    399
  • Table C1. 8XC251SA, SB, SP, SQ SFR Map

    404
  • Table C2. Core SFRs

    405
  • Table C3. I/O Port SFRs

    405
  • Table C4. Serial I/O SFRs

    406
  • Table C5. Timer/Counter and Watchdog Timer SFRs

    406
  • Table C6. Programmable Counter Array (PCA) SFRs...

    407
  • Table C7. Register File

    408