Intel 8XC251SQ User Manual

5-13

Table 5-8 lists the addressing modes for the control instructions.

Relative addressing: The control instruction provides the target address as an 8-bit signed
offset (rel) from the address of the next instruction.

Direct addressing: The control instruction provides a target address, which can have 11 bits
(addr11), 16 bits (addr16), or 24 bits (addr24). The target address is written to the PC.

— addr11: Only the lower 11 bits of the PC are changed; i.e., the target address must be in

the current 2-Kbyte block (the 2-Kbyte block that includes the first byte of the next
instruction).

— addr16: Only the lower 16 bits of the PC are changed; i.e., the target address must be in

the current 64-Kbyte region (the 64-Kbyte region that includes the first byte of the next
instruction).

— addr24: The target address can be anywhere in the 16-Mbyte address space.

Indirect addressing: There are two types of indirect addressing for control instructions:

— For the instructions LCALL @WRj and LJMP @WRj, the target address is in the

current 64-Kbyte region. The 16-bit address in WRj is placed in the lower 16 bits of the
PC. The upper eight bits of the PC remain unchanged from the address of the next
instruction.

— For the instruction JMP @A+DPTR, the sum of the accumulator and DPTR is placed in

the lower 16 bits of the PC, and the upper eight bits of the PC are FF:, which restricts
the target address to the code memory space of the MCS 51 architecture.

Relative, 8-bit relative address (rel)

8

-128 to +127 from first byte of next instruction

Direct, 11-bit target address (addr11)

11

Current 2 Kbytes

Direct, 16-bit target address (addr16)

16

Current 64 Kbytes

Direct, 24-bit target address (addr24)

†

24

00:0000H–FF:FFFFH

Indirect (@WRj)

†

16

Current 64 Kbytes

Indirect (@A+DPTR)

16

64-Kbyte region specified by DPXL (reset 
value = 01H)

†

These modes are not used by instructions in the MCS

® 

51 architecture.