Intel 253668-032US User Manual
19-20 Vol. 3
ARCHITECTURE COMPATIBILITY
FPUs handle all addressing and exception-pointer information, whether in protected
mode or not.
mode or not.
19.18.7.15 FXAM Instruction
With the 32-bit x87 FPUs, if the FPU encounters an empty register when executing
the FXAM instruction, it not generate combinations of C0 through C3 equal to 1101 or
1111. The 16-bit IA-32 math coprocessors may generate these combinations, among
others. This difference has no impact on existing software; it provides a performance
upgrade to provide repeatable results.
the FXAM instruction, it not generate combinations of C0 through C3 equal to 1101 or
1111. The 16-bit IA-32 math coprocessors may generate these combinations, among
others. This difference has no impact on existing software; it provides a performance
upgrade to provide repeatable results.
19.18.7.16 FSAVE and FSTENV Instructions
With the 32-bit x87 FPUs, the address of a memory operand pointer stored by FSAVE
or FSTENV is undefined if the previous floating-point instruction did not refer to
memory
or FSTENV is undefined if the previous floating-point instruction did not refer to
memory
19.18.8 Transcendental
Instructions
The floating-point results of the P6 family and Pentium processors for transcendental
instructions in the core range may differ from the Intel486 processors by about 2 or
3 ulps (see “Transcendental Instruction Accuracy” in Chapter 8, “Programming with
the x87 FPU,” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 1). Condition code flag C1 of the status word may differ as a result. The exact
threshold for underflow and overflow will vary by a few ulps. The P6 family and
Pentium processors’ results will have a worst case error of less than 1 ulp when
rounding to the nearest-even and less than 1.5 ulps when rounding in other modes.
The transcendental instructions are guaranteed to be monotonic, with respect to the
input operands, throughout the domain supported by the instruction.
Transcendental instructions may generate different results in the round-up flag (C1)
on the 32-bit x87 FPUs. The round-up flag is undefined for these instructions on the
16-bit IA-32 math coprocessors. This difference has no impact on existing software.
instructions in the core range may differ from the Intel486 processors by about 2 or
3 ulps (see “Transcendental Instruction Accuracy” in Chapter 8, “Programming with
the x87 FPU,” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 1). Condition code flag C1 of the status word may differ as a result. The exact
threshold for underflow and overflow will vary by a few ulps. The P6 family and
Pentium processors’ results will have a worst case error of less than 1 ulp when
rounding to the nearest-even and less than 1.5 ulps when rounding in other modes.
The transcendental instructions are guaranteed to be monotonic, with respect to the
input operands, throughout the domain supported by the instruction.
Transcendental instructions may generate different results in the round-up flag (C1)
on the 32-bit x87 FPUs. The round-up flag is undefined for these instructions on the
16-bit IA-32 math coprocessors. This difference has no impact on existing software.
19.18.9 Obsolete
Instructions
The 8087 math coprocessor instructions FENI and FDISI and the Intel 287 math
coprocessor instruction FSETPM are treated as integer NOP instructions in the 32-bit
x87 FPUs. If these opcodes are detected in the instruction stream, no specific opera-
tion is performed and no internal states are affected.
coprocessor instruction FSETPM are treated as integer NOP instructions in the 32-bit
x87 FPUs. If these opcodes are detected in the instruction stream, no specific opera-
tion is performed and no internal states are affected.