Intel 253668-032US User Manual
19-22 Vol. 3
ARCHITECTURE COMPATIBILITY
19.20 FPU AND MATH COPROCESSOR INITIALIZATION
Table 9-1 shows the states of the FPUs in the P6 family, Pentium, Intel486 processors
and of the Intel 387 math coprocessor and Intel 287 coprocessor following a power-
up, reset, or INIT, or following the execution of an FINIT/FNINIT instruction. The
following is some additional compatibility information concerning the initialization of
x87 FPUs and math coprocessors.
and of the Intel 387 math coprocessor and Intel 287 coprocessor following a power-
up, reset, or INIT, or following the execution of an FINIT/FNINIT instruction. The
following is some additional compatibility information concerning the initialization of
x87 FPUs and math coprocessors.
19.20.1 Intel
®
387 and Intel
®
287 Math Coprocessor Initialization
Following an Intel386 processor reset, the processor identifies its coprocessor type
(Intel
(Intel
®
287 or Intel
®
387 DX math coprocessor) by sampling its ERROR# input some
time after the falling edge of RESET# signal and before execution of the first floating-
point instruction. The Intel 287 coprocessor keeps its ERROR# output in inactive
state after hardware reset; the Intel 387 coprocessor keeps its ERROR# output in
active state after hardware reset.
Upon hardware reset or execution of the FINIT/FNINIT instruction, the Intel 387
math coprocessor signals an error condition. The P6 family, Pentium, and Intel486
processors, like the Intel 287 coprocessor, do not.
point instruction. The Intel 287 coprocessor keeps its ERROR# output in inactive
state after hardware reset; the Intel 387 coprocessor keeps its ERROR# output in
active state after hardware reset.
Upon hardware reset or execution of the FINIT/FNINIT instruction, the Intel 387
math coprocessor signals an error condition. The P6 family, Pentium, and Intel486
processors, like the Intel 287 coprocessor, do not.
19.20.2 Intel486 SX Processor and Intel 487 SX Math Coprocessor
Initialization
When initializing an Intel486 SX processor and an Intel 487 SX math coprocessor,
the initialization routine should check the presence of the math coprocessor and
should set the FPU related flags (EM, MP, and NE) in control register CR0 accordingly
(see Section 2.5, “Control Registers,” for a complete description of these flags). Table
19-2 gives the recommended settings for these flags when the math coprocessor is
present. The FSTCW instruction will give a value of FFFFH for the Intel486 SX micro-
processor and 037FH for the Intel 487 SX math coprocessor.
the initialization routine should check the presence of the math coprocessor and
should set the FPU related flags (EM, MP, and NE) in control register CR0 accordingly
(see Section 2.5, “Control Registers,” for a complete description of these flags). Table
19-2 gives the recommended settings for these flags when the math coprocessor is
present. The FSTCW instruction will give a value of FFFFH for the Intel486 SX micro-
processor and 037FH for the Intel 487 SX math coprocessor.
The EM and MP flags in register CR0 are interpreted as shown in Table 19-3.
Table 19-2. Recommended Values of the EM, MP, and NE Flags for Intel486 SX
Microprocessor/Intel 487 SX Math Coprocessor System
CR0 Flags
Intel486 SX Processor Only
Intel 487 SX Math Coprocessor Present
EM
1
0
MP
0
1
NE
1
0, for MS-DOS* systems
1, for user-defined exception handler