Intel Pentium M 770 RH80536GE0462M Data Sheet

Datasheet

11

This is the normal operating state for both cores of the processor.

C1/AutoHALT is a low power state entered when the processor core executes the HALT 

instruction. The processor core will transition to the C0 state upon the occurrence of 

SMI#, INIT#, LINT[1:0] (NMI, INTR), or FSB interrupt message. RESET# will cause the 

processor to immediately initialize itself.

A System Management Interrupt (SMI) handler will return execution to either Normal 

state or the AutoHALT Powerdown state. See the Intel® Architecture Software 

Developer's Manual, Volume 3A/3B: System Programming Guide for more information.

The system can generate a STPCLK# while the processor is in the AutoHALT 

Powerdown state. When the system deasserts the STPCLK# interrupt, the processor 

will return execution to the HALT state.

While in AutoHALT Powerdown state, the Intel Pentium Dual-Core processor will 

process bus snoops and snoops from the other core.The processor core will enter a 

snoopable sub-state (not shown in 

) to process the snoop and then return to 

the AutoHALT Powerdown state. 

MWAIT is a low power state entered when the processor core executes the MWAIT 

instruction. Processor behavior in the MWAIT state is identical to the AutoHALT state 

except that there is an additional event that can cause the processor core to return to 

the C0 state: the Monitor event. See the Intel® Architecture Software Developer's 

Manual, Volume 2A/2B: Instruction Set Reference for more information.

Individual cores of the processor can enter the C2 state by initiating a P_LVL2 I/O read 

to the P_BLK or an MWAIT(C2) instruction, but the processor will not issue a Stop Grant 

Acknowledge special bus cycle unless the STPCLK# pin is also asserted.

While in C2 state, the processor will process bus snoops and snoops from the other 

core. The processor core will enter a snoopable sub-state (not shown in 

) to 

process the snoop and then return to the C2 state. 

Core C3 state is a very low power state the processor core can enter while maintaining 

context. Individual cores of the Intel Pentium Dual-Core processor can enter the C3 

state by initiating a P_LVL3 I/O read to the P_BLK or an MWAIT(C3) instruction. Before 

entering the C3 state, the processor core flushes the contents of its L1 caches into the 

processor’s L2 cache. Except for the caches, the processor core maintains all its 

architectural state in the C3 state. The Monitor remains armed if it is configured. All of 

the clocks in the processor core are stopped in the C3 state. 

Because the core’s caches are flushed the processor keeps the core in the C3 state 

when the processor detects a snoop on the FSB or when the other core of the processor 

accesses cacheable memory. The processor core will transition to the C0 state upon the 

occurrence of a Monitor event, SMI#, INIT#, LINT[1:0] (NMI, INTR), or FSB interrupt 

message. RESET# will cause the processor core to immediately initialize itself.