Intel Pentium M 770 RH80536GE0462M Data Sheet
Product codes
RH80536GE0462M
Datasheet
9
Low Power Features
2
Low Power Features
2.1
Clock Control and Low Power States
The processor supports low power states at the core level and the package level. A core
may independently enter the C1/AutoHALT, C1/MWAIT, C2 and C3 low power states.
Package low power states include Normal, Stop Grant, Stop Grant Snoop, Sleep and
Deep Sleep. When both cores are in a common core, low-power state the central power
management logic ensures the entire processor enters the respective package low
power state by initiating a P_LVLx (P_LVL2 and P_LVL3) I/O read to the chipset.
The processor implements two software interfaces for requesting low power states,
MWAIT instruction extensions with sub-state hints and P_LVLx reads to the ACPI P_BLK
register block mapped in the processor’s I/O address space. The P_LVLx I/O reads are
converted to equivalent MWAIT C-state requests inside the processor and do not
directly result in I/O reads on the processor FSB. The monitor address does not need to
be setup before using the P_LVLx I/O read interface. The sub-state hints used for each
P_LVLx read can be configured in a software programmable MSR. If a core encounters a
chipset break event while STPCLK# is asserted, then it asserts the PBE# output signal.
Assertion of PBE# when STPCLK# is asserted indicates to system logic that individual
cores should return to the C0 state and the processor should return to the Normal
state.
shows the core low-power
provides a mapping of core, low-power states to package low power
states.
NOTES:
1.
1.
AutoHALT or MWAIT/C1.
Table 2.
Coordination of Core-Level Low Power States at the Package Level
Resolved
Package State
Single
Core:
Dual Core: Core1 State
C0
C1
1
C2
C3
Core0 /
Functi
onal
Co
re
S
tate
C0
Normal
Normal
Normal
Normal
Normal
C1
1
Normal
Normal
Normal
Normal
Normal
C2
Stop Grant
Normal
Normal
Stop Grant
Stop Grant
C3
Deep Sleep
Normal
Normal
Stop Grant
Deep Sleep