Intel Core 2 Duo U7500 U7500 User Manual

Specification Update 

 21 

Performance monitoring event MISALIGN_MEM_REF (05H) is used to count the 

number of memory accesses that cross an 8-byte boundary and are blocked until 

retirement. Due to this erratum, the performance monitoring event 

MISALIGN_MEM_REF also counts other memory accesses. 

Implication:  The performance monitoring event MISALIGN_MEM_REF may over count. The extent 

of the over counting depends on the number of memory accesses retiring while the 

counter is active. 

Workaround: None identified. 

For the steppings affected, see the Summary Tables of Changes. 

A jump to a busy TSS (Task-State Segment) may cause a #TS (invalid TSS exception) 

instead of a #GP fault (general protection exception). 

Implication:  Operation systems that access a busy TSS may get invalid TSS fault instead of a #GP 

fault. Intel has not observed this erratum with any commercially-available software. 

Workaround: None identified. 

For the steppings affected, see the Summary Tables of Changes. 

Code Segment limit violation may occur on 4-GB limit check when the code stream 

wraps around in a way that one instruction ends at the last byte of the segment and 

the next instruction begins at 0 x 0. 

Implication:  This is a rare condition that may result in a system hang. Intel has not observed this 

erratum with any commercially-available software, or system. 

Workaround: Avoid code that wraps around segment limit. 

For the steppings affected, see the Summary Tables of Changes.