Motorola 700/800-Series User Manual

Functional Description

1-17

The 700/800-series MVME162LX may be operated as an embedded 
controller without the VMEbus interface. For this option, the 
VMEchip2 ASIC and the VMEbus buffers are not populated. Also, 
the bus grant daisy chain and the interrupt acknowledge daisy 
chain have zero-ohm bypass resistors installed.

To support this feature, certain logic in the VMEchip2 has been 
duplicated in the MC2chip. This logic is inhibited in the MC2chip 
when the VMEchip2 is present. The enables for these functions are 
controlled by software and MC2chip hardware initialization. 

Note that MVME162LX models ordered without the VMEbus 
interface are shipped with Flash memory blank (the factory uses the 
VMEbus to program the Flash memory with debugger code). To 
use the 162Bug package, MVME162Bug, be sure that jumper header 
J21 is configured for the EPROM memory map. Refer to Chapters 2 
and 3 for further details.

Contact your local Motorola sales office for ordering information.

The following memory options are used on the different versions of 
700/800-series MVME162LX boards. 

The MVME162LX offers the following DRAM options:

❏

4, 8, or 16MB shared DRAM with programmable parity on a 
mezzanine module

❏

4, 8, 16, or 32MB ECC DRAM on a mezzanine module

The DRAM architecture for non-ECC memory is non-interleaved 
for 4 or 8MB and interleaved for 16MB. Parity protection is enabled 
with interrupts or bus exception when a parity error is detected.