Motorola 700/800-Series User Manual

3-14

Debugger General Information

DRAM can be ECC or parity type. DRAM mezzanines are mapped 
in contiguously starting at zero ($00000000), largest first. With two 
mezzanines of the same size but different type, parity DRAM is 
mapped to the selected base address and the ECC mezzanine will 
follow. If both are ECC type, the bottom one is first.

The 162Bug requires 2KB of NVRAM for storage of board 
configuration, communication, and booting parameters. This 
storage area begins at $FFFC16F8 and ends at $FFFC1EF7 (for 
details, refer to the maps in the MVME162LX Embedded Controller 
ProgrammerÕs Reference Guide). 

162Bug requires a minimum of 64KB of contiguous read/write 
memory to operate. The 

 command controls where this block 

of memory is located. Regardless of where the onboard RAM is 
located, the first 64KB is used for 162Bug stack and static variable 
space and the rest is reserved as user space. Whenever the 
MVME162LX is reset, the target PC is initialized to the address 
corresponding to the beginning of the user space, and the target 
stack pointers are initialized to addresses within the user space, 
with the target Interrupt Stack Pointer (ISP) set to the top of the user 
space. 

A single DRAM mezzanine

$00000000

$FFE00000
(onboard 
SRAM)

A single SRAM mezzanine

N/A

$00000000

A DRAM mezzanine stacked with an SRAM 
mezzanine

$00000000

$E1000000

Two DRAM mezzanines stacked

$00000000

$FFE00000
(onboard 
SRAM)