Intel PCI User Manual

219

The PCI-X specification states that accesses to internal device memory spaces must complete 

within a specific target initial latency, or else the device should signal that it completes the 
transaction later using a split-completion operation. Due to internal access latencies, read accesses 

to most device registers in the Ethernet controller exceeds target initial-access latencies, and 

therefore are split.

Once a register read operation has been split, the device may, as part of normal operation, initiate a 
large inbound or outbound transmit or receive data burst transaction. The split completion for the 

pending register read might be forced to wait until the data burst completes. Therefore, the read 

access-delay for most registers can be indeterminate (although is generally bounded by the nature 
or normal burst transactions).

A small subset of the internal register space has been identified as most critical for high-perfor-

mance driver execution. The variable completion delay for access to some registers could 

potentially limit the performance of such critical routines as Interrupt Service Routines (ISRs). To 
help minimize potential critical routine performance, read accesses to a small subset of internal 

register space will instead complete without being split. These registers are listed as follows: 

1.

Not applicable to the 82540EP/EM, 82541xx, or 82547GI/EI.

General

00000h

CTRL

Device Control Register

General

00008h

STATUS

Device Status Register

General

00010h

EECD

EEPROM/Flash Control/Data Register

General

00018h

CTRL_EXT

Extended Device Control Register

General

00020h

MDIC

MDI Control Register

General

00028h

FCAL

Flow Control Address Low

General

0002Ch

FCAH

Flow Control Address High

General

00030h

FCT

Flow Control Type

General

00038h

VET

VLAN Ether Type

General

00170h

FCTTV

Flow Control Transmit Timer Value

General

00178h

TXCW

Transmit Configuration Word

General

00180h

RXCW

Receive Configuration Word

General

01000h

PBA

Packet Buffer Allocation

Interrupt

000C0h

ICR

Interrupt Cause Read

Interrupt

000C8h

ICS

Interrupt Cause Set