Intel PCI User Manual

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The EEPROM configuration bit “Force CSR Read Split” (Initialization Control Word 2, word 0Fh) 

provides the ability to configure the device to split all internal register accesses, rather than 

providing non-split behavior for the registers listed.

This section contains detailed register descriptions for general purpose, DMA, interrupt, receive, 
and transmit registers. These registers correspond to the main functions of the Ethernet controller.

This register and the Extended Device Control register (CTRL_EXT) control the major operational 

modes for the Ethernet controller. 

While software writes to this register to control device settings, several bits (such as FD and 
SPEED) can be overridden depending on other bit settings and the resultant link configuration 

determined by the PHY’s Auto-Negotiation resolution.

TBI Mode is used only by the 82544GC/EI Ethernet controller. Internal SerDes mode is used only 

by the 82546GB/EB and 82545GM/EM Ethernet controllers.

Interrupt

000D0h

IMS

Interrupt Mask Set/Read

Interrupt

000D8h

IMC

Interrupt Mask Clear

Transmit

00400h

TCTL

Transmit Control