Intel PCI User Manual

317

Since write back of transmit descriptors is optional (under the control of RS bit in the descriptor), 
not all processed descriptors are counted with respect to WTHRESH. Descriptors start accumu-

lating after a descriptor with RS (or RPS for the 82544GC/EI) is set. Furthermore, with transmit 

descriptor bursting enabled, some descriptors are written back that did not have RS (or RPS for the 
82544GC/EI

) set in their respective descriptors.

LWTHRESH (not applicable to the 82544GC/EI) controls the number of pre-fetched transmit 

descriptors at which a transmit descriptor-low interrupt (ICR.TXD_LOW) is reported. This can 

enable software to operate more efficiently by maintaining a continuous addition of transmit work, 
interrupting only when the hardware nears completion of all submitted work. LWTHRESH 

specifies a multiple of eight descriptors. An interrupt is asserted when the number of descriptors 

available transitions from (threshold level=8*LWTHRESH)+1 to (threshold 
level=8*LWTHRESH). Setting this value to 0b causes this interrupt to be generated only when the 

transmit descriptor cache becomes completely empty. 

Reserved

23:22

0b

Reserved
Reads as 0b. Should be written as 0b for future compatibility.

GRAN

24

0b

Granularity
Set the values of PTHRESH, HTHRESH and WTHRESH in units 
of cache lines or descriptors (each descriptor is 16 bytes) 
1b = Descriptor granularity.
0b = Cache line granularity.

LWTHRESH

1

31:25

0h

Transmit descriptor Low Threshold
Interrupt asserted when the number of descriptors pending 
service in the transmit descriptor queue (processing distance 
from the TDT) drops below this threshold.

1.

Not applicable to the 82544GC/EI.

1.

Not applicable to the 82544GC/EI.

Reserved

IDV

IDV

15:0

0b

Interrupt Delay Value
Counts in units of 1.024 

µs. (0b = disabled)

Reserved

31:16

0b

Reads as 0b. Should be written to 0b for future compatibility.