Intel PCI User Manual
Software Developer’s Manual
341
Register Descriptions
Table 13-100. MCC Register Bit Description
13.7.9
Late Collisions Count
LATECOL (04020h; R)
Late collisions are collisions that occur after 64-byte time into the transmission of the packet while
working in 10-100 Mb/s data rate, and 512 byte time into the transmission of the packet while
working in the 1000 Mb/s data rate. This register only increments if transmits are enabled and the
device is in half-duplex mode.
device is in half-duplex mode.
Table 13-101. LATECOL Register Bit Description
13.7.10
Collision Count
COLC (04028h; R)
This register counts the total number of collisions that are not late collisions seen by the transmitter.
This register only increments if transmits are enabled and the Ethernet controller is in half-duplex
This register only increments if transmits are enabled and the Ethernet controller is in half-duplex
mode.
Table 13-102. COLC Register Bit Description
31
0
MCC
Field
Bit(s)
Initial
Value
Value
Description
MCC
31:0
0b
Number of times a successful transmit encountered multiple
collisions.
collisions.
31
0
LCC
Field
Bit(s)
Initial
Value
Value
Description
LCC
31:0
0b
Number of packets with late collisions.
31
0
CCC
Field
Bit(s)
Initial
Value
Value
Description
CCC
31:0
0b
Total number of collisions experienced by the transmitter.