Intel PCI User Manual

342

This register counts defer events. A defer event occurs when the transmitter cannot immediately 
send a packet due to the medium being busy either because another device is transmitting, the IPG 

timer has not expired, half-duplex deferral events, reception of XOFF frames, or the link is not up. 

This register only increments if transmits are enabled. This counter does not increment for 
streaming transmits that are deferred due to TX IPG.

This register counts the number of successful packet transmissions in which the internal carrier 

sense signal from the PHY was not asserted within one slot time of start of transmission.

The PHY should assert the internal carrier sense signal during every transmission. Failure to do so 
may indicate that the link has failed, or the PHY has an incorrect link configuration. This register 

only increments if transmits are enabled. This register is not valid in internal SerDes

1

 mode (TBI 

mode for the 82544GC/EI), and is only valid when the Ethernet controller is operating at full 
duplex.

CDC

CDC

31:0

0b

Number of defer events.

1.

The 82540EP/EM, 82541xx, and 82547GI/EI do not support SerDes functionality.

TNCRS

TNCRS

31:0

0b

Number of transmissions without a CRS assertion from the PHY.