Intel PCI User Manual

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Once activated, hardware fetches the descriptor indicated by the hardware head register. The 
hardware tail register points one beyond the last valid descriptor.

Software can determine if a packet has been sent by setting the RS bit (or the RPS bit for the 

82544GC/EI only) in the transmit descriptor command field. Checking the transmit descriptor DD 

bit in memory eliminates a potential race condition. All descriptor data is written to the IO bus 
prior to incrementing the head register, but a read of the head register could “pass” the data write in 

systems performing IO write buffering. Updates to transmit descriptors use the same IO write path 

and follow all data writes. Consequently, they are not subject to the race condition. Other potential 
conditions also prohibit software reading the head pointer.

In general, hardware prefetches packet data prior to transmission. Hardware typically updates the 

value of the head pointer after storing data in the transmit FIFO

1

.

The process of checking for completed packets consists of one of the following:

•

Scan memory for descriptor status write-backs.

•

Take an interrupt. An interrupt condition can be generated whenever a transmit queue goes 

empty (ICR.TXQE). Interrupts can also be triggered in other ways.

The descriptor processing strategy for transmit descriptors is essentially the same as for receive 
descriptors except that a different set of thresholds are used. As for receives, the number of on-chip 

transmit descriptors buffer space is 64 descriptors. 

When the on-chip buffer is empty, a fetch happens as soon as any descriptors are made available 

(software writes to the tail pointer). When the on-chip buffer is nearly empty 
(TXDCTL.PTHRESH), a prefetch is performed whenever enough valid descriptors 

(TXDCTL.HTHRESH) are available in host memory and no other DMA activity of greater priority 

is pending (descriptor fetches and write-backs or packet data transfers).

The descriptor prefetch policy is aggressive to maximize performance. If descriptors reside in an 
external cache, the system must ensure cache coherency before changing the tail pointer.

When the number of descriptors in host memory is greater than the available on-chip descriptor 

storage, the chip may elect to perform a fetch which is not a multiple of cache line size. The 
hardware performs this non-aligned fetch if doing so results in the next descriptor fetch being 

aligned on a cache line boundary. This allows the descriptor fetch mechanism to be most efficient 

in the cases where it has fallen behind software.

The descriptor write-back policy for transmit descriptors is similar to that for receive descriptors 

with a few additional factors. First, since transmit descriptor write-backs are optional (controlled 

by RS

2

 in the transmit descriptor), only descriptors which have one (or both) of these bits set starts 

the accumulation of write-back descriptors. Secondly, to preserve backward compatibility with the 

82542, if the TXDCTL.WTHRESH value is 0b, the Ethernet controller writes back a single byte of 

the descriptor (TDESCR.STA) and all other bytes of the descriptor are left unchanged. 

1. With the RPS bit set, the head is not advanced until after the packet is transmitted or rejected due to excess collisions (82544GC/EI only).
2. And RPS for the 82544GC/EI only.