Intel PCI User Manual

54

Since the benefit of delaying and then bursting transmit descriptor write-backs is small at best, it is 
likely that the threshold are left at the default value (0b) to force immediate write-back of transmit 

descriptors and to preserve backward compatibility.

Descriptors are written back in one of three conditions:

•

TXDCTL.WTHRESH = 0b and a descriptor which has RS

1

 set is ready to be written back

•

Transmit Interrupt Delay timer expires

•

TXDCTL.WTHRESH > 0b and TXDCTL.WTHRESH descriptors have accumulated

For the first condition, write-backs are immediate. This is the default operation and is backward 

compatible. For this case, the Transmit Interrupt delay function works as described in 

The other two conditions are only valid if descriptor bursting is enabled (see 

). In 

the second condition, the Transmit Interrupt Delay timer (TIDV) is used to force timely write–back 

of descriptors. The first packet after timer initialization starts the timer. Timer expiration flushes 
any accumulated descriptors and sets an interrupt event (TXDW). 

For the final condition, if TXDCTL.WTHRESH descriptors are ready for write-back, the write-

back is performed.

Hardware supplies three transmit interrupts. These interrupts are initiated through the following 
conditions:

•

Transmit queue empty (TXQE) — All descriptors have been processed. The head pointer is 

equal to the tail pointer.

•

Descriptor done [Transmit Descriptor Write-back (TXDW)] — Set when hardware writes 

back a descriptor with RS

1

 set. This is only expected to be used in cases where, for example, 

the streams interface has run out of descriptors and wants to be interrupted whenever progress 
is made.

•

Transmit Delayed Interrupt (TXDW) — In conjunction with IDE (Interrupt Delay Enable), the 
TXDW indication is delayed by a specific time per the TIDV register. This interrupt is set 

when the transmit interrupt countdown register expires. The countdown register is loaded with 

the value of the IDV field of the TIDV register, when a transmit descriptor with its RS

1

 bit and 

the IDE bit are set, is written back. When a Transmit Delayed Interrupt occurs, the TXDW 

interrupt cause bit is set (just as when a Transmit Descriptor Write-back interrupt occurs). This 

interrupt may be masked in the same manner as the TXDW interrupt. This interrupt is used 
frequently by software that performs dynamic transmit chaining, by adding packets one at a 

time to the transmit chain.

Note: The transmit delay interrupt is indicated with the same interrupt bit as the transmit write-back 

interrupt, TXDW. The transmit delay interrupt is only delayed in time as discussed above.

1. Or RPS for the 82544GC/EI only.