Renesas R5S72623 User Manual
Section 25 NAND Flash Memory Controller
R01UH0134EJ0400 Rev. 4.00
Page 1301 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
25.3.4
Address Register (FLADR)
FLADR is a 32-bit readable/writable register that specifies the value to be output as an address.
The address of the size specified by ADRCNT[1:0] in the command control register is output
sequentially from ADR1 in byte units. By the sector access address specification bit (ADRMD) of
the command control register, it is possible to specify whether the sector number set in the address
data bits is converted into an address to be output to the flash memory.
sequentially from ADR1 in byte units. By the sector access address specification bit (ADRMD) of
the command control register, it is possible to specify whether the sector number set in the address
data bits is converted into an address to be output to the flash memory.
When ADRMD = 1
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADR4[7:0]
ADR3[7:0]
ADR2[7:0]
ADR1[7:0]
Bit Bit
Name
Initial
Value R/W
Value R/W
Description
31 to 24 ADR4[7:0] H'00
R/W
Fourth Address Data
Specify 4th data to be output to flash memory as an
address when ADRMD = 1.
address when ADRMD = 1.
23 to 16 ADR3[7:0] H'00
R/W
Third Address Data
Specify 3rd data to be output to flash memory as an
address when ADRMD = 1.
address when ADRMD = 1.
15 to 8
ADR2[7:0] H'00
R/W
Second Address Data
Specify 2nd data to be output to flash memory as an
address when ADRMD = 1.
address when ADRMD = 1.
7 to 0
ADR1[7:0] H'00
R/W
First Address Data
Specify 1st data to be output to flash memory as an
address when ADRMD = 1.
address when ADRMD = 1.