Renesas R5S72623 User Manual
Section 25 NAND Flash Memory Controller
R01UH0134EJ0400 Rev. 4.00
Page 1303 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
25.3.5
Address Register 2 (FLADR2)
FLADR2 is a 32-bit readable/writable register, and is valid when the ADRCNT2 bit in
FLCMDCR is set to 1. FLADR2 specifies an address to be output in command access mode.
FLCMDCR is set to 1. FLADR2 specifies an address to be output in command access mode.
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ADR5[7:0]
Bit Bit
Name
Initial
Value R/W
Value R/W
Description
31 to 8
All
0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
always be 0.
7 to 0
ADR5[7:0] H'00
R/W
Fifth Address Data
Specify 5th data to be output to flash memory as an
address when ADRMD = 1.
address when ADRMD = 1.