Renesas R5S72623 User Manual
Section 26 USB 2.0 Host/Function Module
Page 1418 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
Bit Bit
Name
Initial
Value R/W Description
Value R/W Description
11 to 7
All
0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
should always be 0.
6 to 0
MXPS[6:0]
H'40
R/W
Maximum Packet Size
Specifies the maximum data payload (maximum
packet size) for the DCP.
packet size) for the DCP.
These bits are initialized to H'40 (64 bytes).
These bits should be set to the value based on the
USB Specification.
USB Specification.
These bits should be set while CSSTS is 0 and PID
is NAK.
is NAK.
Before modifying these bits after modifying the PID
bits for the DCP from BUF to NAK, check that
CSSTS and PBUSY are 0. However, if the PID bits
have been modified to NAK by this module,
checking PBUSY is not necessary.
bits for the DCP from BUF to NAK, check that
CSSTS and PBUSY are 0. However, if the PID bits
have been modified to NAK by this module,
checking PBUSY is not necessary.
While MXPS is 0, do not write to the FIFO buffer or
do not set PID to BUF.
do not set PID to BUF.
26.3.30
DCP Control Register (DCPCTR)
DCPCTR is a register that is used to confirm the buffer memory status, change and confirm the
data PID sequence bit, and set the response PID for the DCP.
data PID sequence bit, and set the response PID for the DCP.
This register is initialized by a power-on reset. The CCPL and PID[1:0] bits are initialized by a
USB bus reset.
USB bus reset.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit:
Initial value:
R/W:
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
R
R/W*
1
R
R/W*
1
R
R
R/W*
1
R/W*
2
R/W*
1
R
R
R/W
R
R/W*
1
R/W
R/W
BSTS SUREQ CSCLR CSSTS
SUREQ
CLR
—
—
SQCLR SQSET SQMON PBUSY PINGE
—
CCPL
PID[1:0]