Renesas R5S72623 User Manual
Section 16 Renesas Serial Peripheral Interface
R01UH0134EJ0400 Rev. 4.00
Page 795 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
16.3.9
Data Control Register (SPDCR)
SPDCR selects the width to access SPDR from longword-, word-, and byte-width, and enables or
disables dummy data transmission for the master mode operation.
If the contents of bits other than the TXDMY of SPDCR are changed while bit TEND in the status
register (SPSR) indicates that transmission is not completed, the subsequent operation cannot be
guaranteed.
register (SPSR) indicates that transmission is not completed, the subsequent operation cannot be
guaranteed.
7
6
5
4
3
2
1
0
Bit:
Initial value:
R/W:
0
0
1
0
0
0
0
0
R/W
R/W
R/W
R
R
R
R
R
TXDMY SPLW1 SPLW0
⎯
⎯
⎯
⎯
⎯
Bit Bit
Name
Initial
Value R/W Description
Value R/W Description
7
TXDMY
0
R/W
Dummy Data Transmission Enable
Enables or disables dummy data transmission.
When communication is performed with this bit set to
1, dummy data is transmitted from the MOSI pin and
a serial communication can be performed even if
there is no transmit data in the transmit buffer.
1, dummy data is transmitted from the MOSI pin and
a serial communication can be performed even if
there is no transmit data in the transmit buffer.
Specifically, if there is no transmit data in the
transmit buffer and this bit is set to 1, dummy data is
transferred to the shift register. The dummy data is
undefined.
transmit buffer and this bit is set to 1, dummy data is
transferred to the shift register. The dummy data is
undefined.
0: Disables dummy data transmission.
1: Enables dummy data transmission.
Note: This bit is valid only in the master mode.