Renesas R5S72623 User Manual
Section 16 Renesas Serial Peripheral Interface
R01UH0134EJ0400 Rev. 4.00
Page 797 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
16.3.10
Clock Delay Register (SPCKD)
SPCKD sets a period from the beginning of SSL signal assertion to RSPCK oscillation (RSPCK
delay) when the SCKDEN bit in the command register (SPCMD) is 1. If the contents of SPCKD
are changed while the MSTR and SPE bits in the control register (SPCR) are 1 with the function
of this module enabled in master mode, the subsequent operation cannot be guaranteed.
delay) when the SCKDEN bit in the command register (SPCMD) is 1. If the contents of SPCKD
are changed while the MSTR and SPE bits in the control register (SPCR) are 1 with the function
of this module enabled in master mode, the subsequent operation cannot be guaranteed.
When using this module in slave mode, set B'000 to SCKDL2 to SCKDL0.
7
6
5
4
3
2
1
0
Bit:
Initial value:
R/W:
0
0
0
0
0
0
0
0
R
R
R
R
R
R/W
R/W
R/W
⎯
⎯
⎯
⎯
⎯
SCK
DL2
SCK
DL1
SCK
DL0
Bit Bit
Name
Initial
Value R/W Description
Value R/W Description
7 to 3
All
0
R
Reserved
The write value should always be 0. Otherwise,
operation cannot be guaranteed.
operation cannot be guaranteed.
2
1
0
SCKDL2
SCKDL1
SCKDL0
0
0
0
R/W
R/W
R/W
RSPCK Delay Setting
These bits set an RSPCK delay value when the
SCKDEN bit in SPCMD is 1.
SCKDEN bit in SPCMD is 1.
The relationship between the setting of SCKDL2 to
SCKDL0 and the RSPCK delay value is shown
below.
SCKDL0 and the RSPCK delay value is shown
below.
000: 1 RSPCK
001: 2 RSPCK
010: 3 RSPCK
011: 4 RSPCK
100: 5 RSPCK
101: 6 RSPCK
110: 7 RSPCK
111: 8 RSPCK