Renesas R5S72621 User Manual
Section 19 Serial I/O with FIFO
Page 966 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
(2) Frame Length
The length of the frame to be transferred by this module is specified with the FL3 to FL0 bits in
SIMDR. Table 19.5 shows the relationship between the FL3 to FL0 bit settings and frame length.
SIMDR. Table 19.5 shows the relationship between the FL3 to FL0 bit settings and frame length.
Table 19.5 Frame Length
FL3 to FL0
Slot Length
Number of Bits in a Frame
Transfer Data
00xx
8
8
8-bit monaural data
0100
8
16
8-bit monaural data
0101
8
32
8-bit monaural data
0110
8
64
8-bit monaural data
0111
8
128
8-bit monaural data
10xx
16
16
16-bit monaural data
1100
16
32
16-bit monaural/stereo data
1101
16
64
16-bit monaural/stereo data
1110
16
128
16-bit monaural/stereo data
1111
16
256
16-bit monaural/stereo data
Note: x: Don't care.
(3) Slot Position
This module can specify the position of transmit data and receive data in a frame by slot numbers.
The slot number of each data is specified by the following registers.
The slot number of each data is specified by the following registers.
Transmit data: SITDAR
Receive data: SIRDAR
Receive data: SIRDAR
19.4.4
Register Allocation of Transfer Data
Writing and reading of transmit/receive data is performed for the following registers.
Transmit data writing: SITDR (8-, 16-, or 32-bit access)
Receive data reading: SIRDR (8-, 16-, or 32-bit access)
Figure 19.5 shows the transmit/receive data and the SITDR and SIRDR bit alignment.
Receive data reading: SIRDR (8-, 16-, or 32-bit access)
Figure 19.5 shows the transmit/receive data and the SITDR and SIRDR bit alignment.