Renesas R5S72621 User Manual
Section 19 Serial I/O with FIFO
Page 968 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
Table 19.7 Audio Mode Specification for Receive Data
Mode
Bit
RDLE RDRE
Monaural 1 0
Stereo 1
1
Note: Left and right same audio mode is not supported in receive data.
To execute monaural transmission or reception, use the left channel.
19.4.5
FIFO
(1) Overview
The transmit and receive FIFOs of this module have the following features.
16-stage 32-bit FIFOs for transmission and reception
One FIFO buffer stage is used regardless of the access size. (One-stage 32-bit FIFO access
One FIFO buffer stage is used regardless of the access size. (One-stage 32-bit FIFO access
cannot be divided into multiple accesses.)
(2) Transfer Request
The following FIFO transfer requests can be issued to the CPU or direct memory access
controller.
controller.
Transmit request: TDREQ (transmit FIFO transfer request)
Receive request: RDREQ (receive FIFO transfer request)
The conditions to issue the transmit/receive FIFO transfer requests can be specified individually.
The transmit request condition is specified with the TFWM2 to TFWM0 bits in SIFCTR, and the
receive FIFO transfer request is specified with the RFWM2 to RFWM0 bits in SIFCTR. Tables
19.8 and 19.9 summarize the conditions specified by SIFCTR.
Receive request: RDREQ (receive FIFO transfer request)
The conditions to issue the transmit/receive FIFO transfer requests can be specified individually.
The transmit request condition is specified with the TFWM2 to TFWM0 bits in SIFCTR, and the
receive FIFO transfer request is specified with the RFWM2 to RFWM0 bits in SIFCTR. Tables
19.8 and 19.9 summarize the conditions specified by SIFCTR.