Renesas R5S72621 User Manual
Section 23 CD-ROM Decoder
Page 1200 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
23.3.1
Enable Control Register (CROMEN)
The enable control register (CROMEN) enables subcode processing and CD-ROM decoding, and
stops CD-ROM decoding forcibly.
stops CD-ROM decoding forcibly.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
Initial value:
R/W:
SUBC_
EN
CROM_
EN
CROM_
STP
-
-
-
-
-
Bit Bit
Name
Initial
Value R/W
Value R/W
Description
7
SUBC_EN 0
R/W
Subcode Processing Enable
This bit should be set and cleared simultaneously with
CROM_EN. It is automatically cleared when decoding
is automatically stopped due to an abnormal condition
or when CROM_STP = 1
is automatically stopped due to an abnormal condition
or when CROM_STP = 1
6
CROM_EN 0
R/W
CD-ROM Decoding Enable
When this bit is set to 1, CD-ROM decoding starts after
detection of a valid sync code. When the bit is cleared
to 0, decoding stops on completion of the processing for
the sector currently being decoded.
detection of a valid sync code. When the bit is cleared
to 0, decoding stops on completion of the processing for
the sector currently being decoded.
This bit is automatically cleared when the automatic
decode-stopping function woks or when CROM_STP =
1.
decode-stopping function woks or when CROM_STP =
1.
5 CROM_
STP
0
R/W
Forcible Stop of CD-ROM Decoding
When this bit is set to 1, CD-ROM decoding is stopped
immediately and the SUBC_EN and CROM_EN bits are
automatically reset to 0. Before decoding can resume,
this bit must be cleared to 0.
immediately and the SUBC_EN and CROM_EN bits are
automatically reset to 0. Before decoding can resume,
this bit must be cleared to 0.
4 to 0
All
0
R/W
Reserved
These bits are always read as 0.The write value should
always be 0.
always be 0.