Renesas R5S72621 User Manual
Section 23 CD-ROM Decoder
R01UH0134EJ0400 Rev. 4.00
Page 1205 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit
Name
Initial
Value R/W
Value R/W
Description
6 to 4
MD_DEC
[2:0]
[2:0]
101
R/W
EDC/ECC Checking Mode Select
000: No checking
001: EDC only
010: Q correction + EDC
011: P correction + EDC
100: QP correction + EDC
101: PQ correction + EDC
110: Setting prohibited
111: Setting prohibited
3, 2
All
0
R/W
Reserved
These bits are always read as 0. The write value should
always be 0.
always be 0.
1, 0
MD_
PQREP
[1:0]
PQREP
[1:0]
01
R/W
Number of Iterations of PQ or QP Correction
Number of correction iterations when PQ- or QP-
correction is specified by MD_DEC[2:0].
correction is specified by MD_DEC[2:0].
00: Setting prohibited
01: One iteration
10: Two iterations
11: Three iterations
23.3.5
Automatic Decoding Stop Control Register (CROMCTL3)
The automatic decoding stop control register (CROMCTL3) is used to select abnormal conditions
on which decoding will be automatically stopped. When decoding is stopped in response to any of
the selected conditions, an IBUF interrupt is generated and the condition is indicated in the
CBUFST1 register. The setting of this register becomes valid at the sector-to-sector transition
on which decoding will be automatically stopped. When decoding is stopped in response to any of
the selected conditions, an IBUF interrupt is generated and the condition is indicated in the
CBUFST1 register. The setting of this register becomes valid at the sector-to-sector transition
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
Initial value:
R/W:
STP_
ECC
STP_
EDC
-
STP_
MD
STP_
MIN
-
-
-