Renesas R5S72621 User Manual
Section 23 CD-ROM Decoder
Page 1206 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
Bit Bit
Name
Initial
Value R/W
Value R/W
Description
7
STP_ECC
0
R/W
When this bit is set to 1, decoding is stopped if an error
is found to be not correctable by ECC correction.
is found to be not correctable by ECC correction.
6
STP_EDC
0
R/W
When this bit is set to 1, decoding is stopped if post-
correction EDC checking indicates an error.
correction EDC checking indicates an error.
5
0 R/W
Reserved
This bit is always read as 0. The write value should
always be 0.
always be 0.
4
STP_MD
0
R/W
When this bit is set to 1, decoding is stopped if the
sector has a mode or form setting that does not match
those of the immediately preceding sector.
sector has a mode or form setting that does not match
those of the immediately preceding sector.
3
STP_MIN
0
R/W
When this bit is set to 1, decoding is stopped if a non-
sequential minutes, seconds, or frames (1/75 second)
value is encountered.
sequential minutes, seconds, or frames (1/75 second)
value is encountered.
2 to 0
All
0
R/W
Reserved
These bits are always read as 0. The write value should
always be 0.
always be 0.
23.3.6
Decoding Option Setting Control Register (CROMCTL4)
The decoding option setting control register (CROMCTL4) enables/disables buffering control at
link block detection, specifies the information indicated by the status register, and controls the
ECC correction mode. The setting of this register becomes valid at the sector-to-sector transition
link block detection, specifies the information indicated by the status register, and controls the
ECC correction mode. The setting of this register becomes valid at the sector-to-sector transition
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
Initial value:
R/W:
-
LINK2
-
ER0SEL NO_ECC
-
-
-