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Renesas R5S72621 User Manual

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Section 23   CD-ROM Decoder 
Page 1238 of 2108 
 
R01UH0134EJ0400  Rev. 4.00 
 
 Sep 
24, 
2014 
SH7262 Group, SH7264 Group
23.3.49
  Interrupt Flag Register (INTHOLD) 
The interrupt flag register (INTHOLD) consists of various interrupt flags. 
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
Initial value:
R/W:
ISEC
ITARG
ISY
IERR
IBUF
IREADY
-
-
 
 
Bit Bit 
Name 
Initial 
Value 
R/W Description 
7 
ISEC 
0 
R/W 
ISEC Interrupt Flag 
Writing 0 to this bit is only possible after 1 has been 
read from it. 
6 
ITARG 
0 
R/W 
ITARG Interrupt Flag 
Writing 0 to this bit is only possible after 1 has been 
read from it. 
5 
ISY 
0 
R/W 
ISY Interrupt Flag 
Writing 0 to this bit is only possible after 1 has been 
read from it. 
4 
IERR 
0 
R/W 
IERR Interrupt Flag 
Writing 0 to this bit is only possible after 1 has been 
read from it. 
3 
IBUF 
0 
R/W 
IBUF Interrupt Flag 
Writing 0 to this bit is only possible after 1 has been 
read from it. 
2 
IREADY 
0 
R/W 
IREADY Interrupt Flag 
Writing 0 to this bit is only possible after 1 has been 
read from it. 
1, 0 
 All 
0 
R/W 
Reserved 
These bits are always read as 0. The write value should 
always be 0.