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Renesas R5S72621 User Manual

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Section 23   CD-ROM Decoder 
R01UH0134EJ0400  Rev. 4.00  
 
Page 1239 of 2108 
Sep 24, 2014 
 
 
 
SH7262 Group, SH7264 Group 
23.3.50
  Interrupt Source Mask Control Register (INHINT) 
The interrupt source mask control register (INHINT) controls masking of various interrupt 
requests in the CD-ROM decoder. 
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
Initial value:
R/W:
INH 
ISEC
INH 
ITARG
INH 
ISY
INH 
IERR
INH 
IBUF
INH 
IREADY
PREINH 
REQDM
PREINH 
IREADY
 
 
Bit Bit 
Name 
Initial 
Value R/W 
Description 
7 
INHISEC 
0 
R/W 
ISEC Interrupt Mask 
When set to 1, inhibits ISEC interrupt requests 
6 
INHITARG  0 
R/W 
ITARG Interrupt Mask 
When set to 1, inhibits ITARG interrupt requests 
5 
INHISY 
0 
R/W 
ISY Interrupt Mask 
When set to 1, inhibits ISY interrupt requests 
4 
INHIERR 
0 
R/W 
IERR Interrupt Mask 
When set to 1, inhibits IERR interrupt requests  
3 
INHIBUF 
0 
R/W 
IBUF Interrupt Mask 
When set to 1, inhibits IBUF interrupt requests 
2 
INHIREADY 
0 
R/W 
IREADY Interrupt Mask 
When set to 1, inhibits IREADY interrupt requests 
1 PREINH 
REQDM 
0 
R/W 
Inhibits setting of the DMA-transfer-request interrupt 
source flag for the output data stream. 
When this bit is set to 1, the DMA-transfer-request 
interrupt source is not retained.  
0 PREINH 
IREADY 
0 
R/W 
Inhibits setting of the IREADY interrupt flag. 
When this bit is set to 1, the IREADY interrupt source 
not retained.