Renesas R5S72621 User Manual
Section 27 Video Display Controller 3
R01UH0134EJ0400 Rev. 4.00
Page 1581 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
27.7.6
Horizontal Valid Video Start Position Register (VIDEO_HSTART)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
1
0
0
0
1
0
1
0
0
R
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VIDEO_HSTART[8:0]
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
Bit Bit
Name
Initial
Value R/W Description
Value R/W Description
31 to 9
All
0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
should always be 0.
8 to 0
VIDEO_
HSTART[8:0]
HSTART[8:0]
H'114
R/W
These bits specify in number of DV_CLK cycles
the horizontal start position of the valid video in
the field.
the horizontal start position of the valid video in
the field.
Note: Capture does not occur when the right edge of video has been cut.