Renesas R5S72621 User Manual
Section 37 Electrical Characteristics
R01UH0134EJ0400 Rev. 4.00
Page 1981 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
37.4.3
Bus Timing
Table 37.7 Bus Timing
B
= 72 MHz*
1
Item Symbol
Min.
Max.
Unit
Figure
Address delay time 1
t
AD1
0/2*
3
10.5 ns
Figures
37.9 to
37.33, 37.36 to 37.39
Address delay time 2
t
AD2
1/2t
cyc
1/2t
cyc
+ 10.5 ns
Figure 37.16
Address delay time 3
t
AD3
1/2t
cyc
1/2t
cyc
+ 10.5 ns
Figures 37.34, 37.35
Address setup time
t
AS
0
ns
Figures 37.9 to
37.12, 37.16
37.12, 37.16
Chip enable setup time
t
CS
0
ns
Figures 37.9 to
37.12, 37.16
37.12, 37.16
Address hold time
t
AH
0
ns
Figures 37.9 to 37.12
BS delay time
t
BSD
10.5
ns
Figures 37.9 to
37.30, 37.34, 37.36
to 37.39
37.30, 37.34, 37.36
to 37.39
CS delay time 1
t
CSD1
0/2*
3
10.5
ns
Figures 37.9 to
37.33, 37.36 to 37.39
37.33, 37.36 to 37.39
CS delay time 2
t
CSD2
1/2t
cyc
1/2t
cyc
+ 10.5 ns
Figures 37.34, 37.35
Read write delay time 1
t
RWD1
0/2*
3
10.5
ns
Figures 37.9 to
37.33, 37.36 to 37.39
37.33, 37.36 to 37.39
Read write delay time 2
t
RWD2
1/2t
cyc
1/2t
cyc
+ 10.5 ns
Figures 37.34, 37.35
Read strobe delay time
t
RSD
1/2t
cyc
1/2t
cyc
+ 10.5 ns
Figures 37.9 to
37.16, 37.36, 37.37
37.16, 37.36, 37.37
Read data setup time 1
t
RDS1
1/2t
cyc
+ 4
ns
Figures 37.9 to
37.15, 37.36 to 37.39
37.15, 37.36 to 37.39